similar to: lapply, strsplit, and list elements

#I would like to use the below data to make a scatter plot matrix with #code similar to that below the data #conceptually this is the right approach I think #thanks in advance melt.gg <- structure(list(stream = c("Bonham Lower", "Bonham Lower", "Bonham Lower", "Bonham Lower", "Bonham Lower", "Bonham Lower", "Bonham Lower",

Hello, I have a question related to recursive partitioning, but I cannot find an answer, likely because I don't know how to properly word my Google search query. All recursive partitioning examples, which I can find, are used for either classification or regression trees like library(tree) data(iris) tree(Species ~ Sepal.Width + Petal.Width, data = iris) which implies building a

I am an R beginner and trying to run a SUR model in R framework. subset(esasp500, Obs <=449 & Obs>=197, select = -Date) ->ev13sub c(Obs>=397) & c(Obs<=399) ->d13 c(Obs>=400) & c(Obs<=449) ->f13 SP500*f13 ->SP500f13 BBC~SP500+d13+SP500f13 ->sur132 BOW~SP500+d13+SP500f13 ->sur133 CSK~SP500+d13+SP500f13 ->sur134

Dear Admin, I will appreciate if you advise me an effective way to write the following R code including nested for loops. I cannot do it by using expand.grid function because it results with memory allocation problems. Thanks for your time and consideration. for(d1 in 0:n){ for(d2 in 0:n){ for(d3 in 0:n){ for(d4 in 0:n){ for(d5 in 0:n){ for(d6 in 0:n){ for(d7 in 0:n){ for(d8 in 0:n){ for(d9 in

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

Hi Alexander, thanks for your good work on the megatec_usb driver. I have made a few more (cosmetic) changes. Is the driver now working stably for your device? In particular, do the instant commands (and particularly "upsdrvctl -k") work properly? In this case, we could hopefully mark the device as "supported" and merge the driver to the main branch. There is still the

To reduce memory consumption clobbered registers are handled with RegisterMask machine operands which contain a bitset of all registers clobbered. - Matthias > On Jul 29, 2015, at 3:00 PM, Daniel Sanders <daniel.sanders at imgtec.com> wrote: > > I believe I've identified the problem with almabench but I haven't found the root cause in the compiler yet. > > The

Dear R-Helpers: I am using trying to use *ddply* to extract min and max of a particular column in a data.frame. I am using two different forms of the function: ## var_name_to_split is a string -- something like "var1" which is the name of a column in data.frame ddply( df, .(as.name(var_name_to_split)), function(x) c(min(x[ , 3] , max(x[ , 3]))) ## fails with an error - case 1 ddply(

hi all, I'm full of questions today :). Thanks in advance for your help! Here's the problem: x <- c('18x.6','12x.9','302x.3') I want to get a vector that is c('18x','12x','302x') This is easily done using this code: unlist(lapply(strsplit(x,".",fixed=TRUE),function(x) x[1])) So far so good. The problem is that x is a vector

Thanks. This is making a lot more sense now and it's looking like this issue isn't Mips specific. Here's the IR dump before simple register coalescing (note: I've patched the IR printer to print the contents of the regmask): 4480B %vreg260<def> = LDC1 %vreg253, <cp#3>[TF=6]; mem:LD8[ConstantPool] AFGR64:%vreg260 GPR32:%vreg253 4496B %vreg261<def> = FMUL_D32

Hello All, I run into this problem when I modify seabios. (XEN) hvm.c:1131:d13 Triple fault on VCPU 0 - invoking HVM system reset. Since there is no fault handlers in the early stages of guest boot I am in the need to debug the domain builder, upstream qemu and/or hvmloader to see where exactly the fault is being generated. I have no experience on debugging and this seems like a good time to

> This isn't really my area of expertise, but I think you're messing up > your RegisterClass definition. Look at how ARM defines DTriple. DTriple is untyped :) , because we do not have any valut type which defines 3xi64. However, the paired register needs to have type. Fabian, what are the definitions of ER and DR register classes? -- With best regards, Anton Korobeynikov Faculty

Fabian, > here are the definitions of these register classes: > > // Data register class > def DR : RegisterClass<"TriCore", [i32], 32, > (add D0, D1, D2, D3, D4, D5, D6, D7, > D8, D9, D10, D11, D12, D13, D14, D15)>; > > // Extended-size data register class > def ER :

Hello, When I run LLC with option "-O0 -march=sparc" on following testcase, fast register allocator crashes with "UNREACHABLE executed" error. LLC generates code successfully with other standard register allocators available. $ cat call.ll define void @test() nounwind { entry: %0 = tail call i32 (...)* @foo() nounwind tail call void (...)* @bar() nounwind ret void }

Hi there, I would like to use my linux system's fgrep to search for a text pattern in a file. Calling system with system("fgrep \"SearchPattern\" /path/to/the/textFile.txt") works in general, but I need to search for the search pattern at the beginning of the line. The corresponding shell command fgrep "^SearchPattern" /path/to/the/textFile.txt

Hi Anton, You're right it fails with a different message with llc 3.0. Anyway thanks for your help. Best Regards Seb > -----Original Message----- > From: Anton Korobeynikov [mailto:anton at korobeynikov.info] > Sent: Monday, June 25, 2012 3:39 PM > To: Sebastien DELDON-GNB > Cc: LLVMdev at cs.uiuc.edu; Rotem, Nadav > Subject: Re: RE : [LLVMdev] Is llc broken for Cortex-A9

Yeah:) I''d like to work on this. Here are my first observations: - We need to call vdev_op_asize method with additonal ''offset'' argument, - We need to move data to new disk starting from the very begining, so we can''t reuse scrub/resilver code which does tree-walk through the data. Below you can see how I imagine to extend RAIDZ. Here is the legend:

Hi Fabian, Anton, On 22/08/2012 08:25, Fabian Scheler wrote: >>> here are the definitions of these register classes: >>> >>> // Data register class >>> def DR : RegisterClass<"TriCore", [i32], 32, >>> (add D0, D1, D2, D3, D4, D5, D6, D7, >>> D8, D9, D10, D11, D12, D13, D14,

2012/8/21 Anton Korobeynikov <anton at korobeynikov.info>: >> This isn't really my area of expertise, but I think you're messing up >> your RegisterClass definition. Look at how ARM defines DTriple. > DTriple is untyped :) , because we do not have any valut type which > defines 3xi64. > However, the paired register needs to have type. > > Fabian, what are

I'm writing a function and keep getting the following error message. myfunc <- function(lst) { lst <- list(roots = c("car insurance", "auto insurance"), roots2 = c("insurance"), prefix = c("cheap", "budget"), prefix2 = c("low cost"), suffix = c("quote", "quotes"), suffix2 = c("rate",