similar to: FW: need some help

Hi , > df Session_Setup DCT FwdDataVols_bin counts Comp 1 User_Initiated NoRLL 1 5058 User_Initiated+NoRLL+1 2 User_Initiated NoRLL 2 584 User_Initiated+NoRLL+2 3 User_Initiated NoRLL 3 191 User_Initiated+NoRLL+3 4 User_Initiated NoRLL 4 128 User_Initiated+NoRLL+4 5 User_Initiated

Df contains Session_Setup DCT RevDataVols_bin counts comp 1 Session_Setup RLL 1 NA Session_Setup+RLL+1 2 Session_Setup RLL 2 NA Session_Setup+RLL+2 3 Session_Setup RLL 3 NA Session_Setup+RLL+3 4 Session_Setup RLL 4 NA Session_Setup+RLL+4 5 Session_Setup RLL 5

Hi All, Let say > df Session_Setup DCT FwdDataVols_bin counts 761 0 1 1 87162 762 0 1 2 11495 763 0 1 3 3986 764 0 1 4 1583 765 0 1 5 920 766 0 1 6 920 767 0 1

Hi, Browse[1]> d4 EVDO_Rev Session_Setup FCA bin counts 50 NA 0 5 1 1 51 NA 0 5 2 1 52 NA 0 5 3 1 53 NA 0 5 4 1 54 NA 0 5 5 1 55 NA 0 5 6 1 56 NA 0 5 7 1 57 NA 0 5 8

Here http://lists.xiph.org/pipermail/theora/2004-September/000619.html Andrey describe encoder structure, this like: "I see the following structure of the compressor implemented in the FPGA (Xilinx Spartan 3 1000K gates): 1. Data from the external frame buffer (FB) memory goes to the Bayer-to-YCbCr (4:2:0) converter in overlapping 20x20 tiles that produce 6 8x8 blocks (one macroblock) on the

I am trying to learn something of the algorithms used in Vorbis. One of them is the "Modified Discrete Cosine Transform" (MDCT). I have found a couple of books with brief descriptions of the DCT, but almost nothing about MDCT. (1) is there just one Modified DCT, which can be expected to be the same whenever someone uses that name, or does it just mean that you have changed

...as promised. This describes the mdct used in my d.m.l patch. I think it is the same as the Lee fast-dct. I typed it in a kind of pseudo-TeX, 'cause the ascii art would kill me. Hope you can read TeX source; if not, ask someone who can to make a .ps/.gif/.whatever of the TeX output, and put it on a webpage or something. I'm to lazy to do it (and besides, I don't have access to TeX,

Correction: Also dlt uses the default timezone, but POSIXlt is not recalculated whereas POSIXct is. Reason for that is the different way values are stored (hours, minutes, seconds as opposed to minutes from origin, as explained in my previous mail) CHeers Joris On Thu, May 18, 2017 at 1:45 PM, Joris Meys <jorismeys at gmail.com> wrote: > This has to do with your own timezone. If I run

> On 18 May 2017, at 14:51, peter dalgaard <pdalgd at gmail.com> wrote: > > >> On 18 May 2017, at 13:47 , Joris Meys <jorismeys at gmail.com> wrote: >> >> Correction: Also dlt uses the default timezone, but POSIXlt is not recalculated whereas POSIXct is. Reason for that is the different way values are stored (hours, minutes, seconds as opposed to minutes

This has to do with your own timezone. If I run that code on my computer, both formats are correct. If I do this after Sys.setenv(TZ = "UTC") Then: > cbind(format(dlt), format(dct)) [,1] [,2] [1,] "2016-12-06 21:45:41" "2016-12-06 20:45:41" [2,] "2016-12-06 21:45:42" "2016-12-06 20:45:42" The reason for that, is that

> On 18 May 2017, at 14:58 , Martyn Plummer <plummerM at iarc.fr> wrote: > > > >> On 18 May 2017, at 14:51, peter dalgaard <pdalgd at gmail.com> wrote: >> >> >>> On 18 May 2017, at 13:47 , Joris Meys <jorismeys at gmail.com> wrote: >>> >>> Correction: Also dlt uses the default timezone, but POSIXlt is not recalculated

> On 18 May 2017, at 13:47 , Joris Meys <jorismeys at gmail.com> wrote: > > Correction: Also dlt uses the default timezone, but POSIXlt is not recalculated whereas POSIXct is. Reason for that is the different way values are stored (hours, minutes, seconds as opposed to minutes from origin, as explained in my previous mail) > I would suspect that there is something more subtle

Good day! I'm creating HDL IP CORE (for using in FPGA) for theora encoder (now only I-frames). I don't undestand one moment. Now i develop such stages: 1. From RBG(byer) to YCbCr converter 2. DCT processing (8x8 pixels blocks) 3. Quantizator of DCT coeff. 4. Zig-Zag of quantized DCT coeff. and now i have uresolved last stage of compression - how i must send 8x8 blocks to huffman

(Disclaimer: this is not an LPC vs. LSP question) After looking at the Vorbis code I was wondering why you were using LSP to quantize the spectral envelope instead of simply quantizing the cepstrum (DCT(log(envelope))) or modified cepstrum (DCT(envelope.^alpha)). To me it seems like when the information is already in the frequency domain, there's no need to go back to LPC. Also, I think a DCT

After installing R-3.4.0 I ran 'make check' which halted here: $ > tail reg-tests-1d.Rout.fail -n 16 > ## format()ing invalid hand-constructed POSIXlt objects > d <- as.POSIXlt("2016-12-06"); d$zone <- 1 > tools::assertError(format(d)) > d$zone <- NULL > stopifnot(identical(format(d),"2016-12-06")) > d$zone <- "CET" # =

After installing R-3.4.0 I ran 'make check' which halted here: $ > tail reg-tests-1d.Rout.fail -n 16 > ## format()ing invalid hand-constructed POSIXlt objects > d <- as.POSIXlt("2016-12-06"); d$zone <- 1 > tools::assertError(format(d)) > d$zone <- NULL > stopifnot(identical(format(d),"2016-12-06")) > d$zone <- "CET" # =

Could someone help me on this please? -----Original Message----- From: r-help-bounces at r-project.org [mailto:r-help-bounces at r-project.org] On Behalf Of Dwaipayan Dasgupta Sent: Thursday, May 03, 2012 1:43 PM To: r-help at r-project.org Subject: [R] Validation of logistic models in R 2.12 Hi everyone, I am trying to validate a logistic model built in R. Not my version of R is 2.12 and I

---------- Forwarded message ---------- From: digital design <developer.fpga at gmail.com> Date: 21 March 2011 13:38 Subject: Re: [theora] alghorithm of working encoder in libtheora To: bens at alum.mit.edu Cc: Reply-All at xiph.org On 18 March 2011 23:15, Benjamin M. Schwartz <bmschwar at fas.harvard.edu>wrote: > On 03/18/2011 01:44 PM, digital design wrote: > > Now i

> On 18 May 2017, at 11:00 , Patrick Connolly <p_connolly at slingshot.co.nz> wrote: > > On Wed, 17-May-2017 at 01:21PM +0200, Peter Dalgaard wrote: > > |> > |> Anyways, you might want to > |> > |> a) move the discussion to R-devel > |> b) include your platform (hardware, OS) and time zone info > > System: Host: MTA-V1-427894 Kernel:

On Wed, 17-May-2017 at 01:21PM +0200, Peter Dalgaard wrote: |> |> Anyways, you might want to |> |> a) move the discussion to R-devel |> b) include your platform (hardware, OS) and time zone info System: Host: MTA-V1-427894 Kernel: 3.19.0-32-generic x86_64 (64 bit gcc: 4.8.2) Desktop: KDE Plasma 4.14.2 (Qt 4.8.6) Distro: Linux Mint 17.3 Rosa Machine: System: