Displaying 20 results from an estimated 3000 matches similar to: "strange (to me) p-value distribution"
2008 Nov 17
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
I have a very strange and complicate H/W platform.
It has many registers in one format.
The register format is:
------------------------------
----------------------------------------------------------------------------------------
| 24-bit | 24-bit |
24-bit | 24-bit |
2008 Nov 20
4
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
Because each channel contains 24-bit, so.. what is the
llvm::SimpleValueType I should use for each channel?
the current llvm::SimpleValueType contains i1, i8, i16, i32, i64, f32,
f64, f80, none of them are fit one channel (24-bit).
I think I can use i32 or f32 to represent each 24-bit channel, if the
runtime result of some machine instructions exceeds 23-bit (1 bit is
for sign), then it is an
2008 Nov 18
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
Why not model each channel as a separate physical register?
Evan
On Nov 17, 2008, at 6:36 AM, Wei wrote:
> I have a very strange and complicate H/W platform.
> It has many registers in one format.
> The register format is:
>
> ------------------------------
> ----------------------------------------------------------------------------------------
> | 24-bit
2003 Dec 29
1
Agent setup
Dear Group,
I have been successful in setting up the Agents, queues and getting agents
to log in.
Is there a way that I could configure the system so that the agent is called
back. i.e. the agent logs into the system, a call is destined for them and
their phone rings.
If some one has this setup I would be very interested in hearing from them.
Warm Regards and Thanks
---------------
Shad
2008 Nov 21
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
24 bit is not unusual in the DSP world. I suppose int == 24 bit
integer for some of these chips?
There isn't a i24 simple type. However, you can create an extended
integer type. See getExtendedIntegerVT. It's almost guaranteed you
will have to change a chunk of target independent codegen to support
the use of an extended type though.
Evan
On Nov 20, 2008, at 4:46 AM, Wei wrote:
2008 Nov 20
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
This is similar to ATI's R300/R420 pixel shaders. I'm familiar with
this hardware, but not really an LLVM expert (working on a code
generator myself, but learning as I go).
Do you have 24-bit integer operations, or just floating point?
What about load/store?
Are you looking to run large C programs with complex data structures,
or just comparatively simple math functions (i.e. a
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
Do you mean MVT::getIntegerVT? Because I can not find
getExtendedIntegerVT in the llvm source codes.
I am excited seeing this function, however I have the following more
questions.
1) You mention I will have to change not small amount of target
indenpendent codegen codes to support this extended type.
Are there any document to describe how to do such kind modification?
I see there is a
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
I have 24-bit integer operations as well as 24-bit floating point
(s7.16) operations.
The H/W supports load/store instructions, however, they does suggest
us not to use these load/store instructions besides debugging purpose.
That is to say, you can imagine we don't have load/store instructions,
we don't have memory, we just have registers.
I will run OpenGL shading laugnage programs on
2018 Mar 13
32
[PATCH v2 00/27] x86: PIE support and option to extend KASLR randomization
Changes:
- patch v2:
- Adapt patch to work post KPTI and compiler changes
- Redo all performance testing with latest configs and compilers
- Simplify mov macro on PIE (MOVABS now)
- Reduce GOT footprint
- patch v1:
- Simplify ftrace implementation.
- Use gcc mstack-protector-guard-reg=%gs with PIE when possible.
- rfc v3:
- Use --emit-relocs instead of -pie to reduce
2018 Mar 13
32
[PATCH v2 00/27] x86: PIE support and option to extend KASLR randomization
Changes:
- patch v2:
- Adapt patch to work post KPTI and compiler changes
- Redo all performance testing with latest configs and compilers
- Simplify mov macro on PIE (MOVABS now)
- Reduce GOT footprint
- patch v1:
- Simplify ftrace implementation.
- Use gcc mstack-protector-guard-reg=%gs with PIE when possible.
- rfc v3:
- Use --emit-relocs instead of -pie to reduce
2017 Oct 04
28
x86: PIE support and option to extend KASLR randomization
These patches make the changes necessary to build the kernel as Position
Independent Executable (PIE) on x86_64. A PIE kernel can be relocated below
the top 2G of the virtual address space. It allows to optionally extend the
KASLR randomization range from 1G to 3G.
Thanks a lot to Ard Biesheuvel & Kees Cook on their feedback on compiler
changes, PIE support and KASLR in general. Thanks to
2017 Oct 04
28
x86: PIE support and option to extend KASLR randomization
These patches make the changes necessary to build the kernel as Position
Independent Executable (PIE) on x86_64. A PIE kernel can be relocated below
the top 2G of the virtual address space. It allows to optionally extend the
KASLR randomization range from 1G to 3G.
Thanks a lot to Ard Biesheuvel & Kees Cook on their feedback on compiler
changes, PIE support and KASLR in general. Thanks to
2018 May 23
33
[PATCH v3 00/27] x86: PIE support and option to extend KASLR randomization
Changes:
- patch v3:
- Update on message to describe longer term PIE goal.
- Minor change on ftrace if condition.
- Changed code using xchgq.
- patch v2:
- Adapt patch to work post KPTI and compiler changes
- Redo all performance testing with latest configs and compilers
- Simplify mov macro on PIE (MOVABS now)
- Reduce GOT footprint
- patch v1:
- Simplify ftrace
2008 Nov 22
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
On Nov 22, 2008, at 11:03 AM, Wei wrote:
> I have 24-bit integer operations as well as 24-bit floating point
> (s7.16) operations.
>
> The H/W supports load/store instructions, however, they does suggest
> us not to use these load/store instructions besides debugging purpose.
> That is to say, you can imagine we don't have load/store instructions,
> we don't have
2017 Oct 11
32
[PATCH v1 00/27] x86: PIE support and option to extend KASLR randomization
Changes:
- patch v1:
- Simplify ftrace implementation.
- Use gcc mstack-protector-guard-reg=%gs with PIE when possible.
- rfc v3:
- Use --emit-relocs instead of -pie to reduce dynamic relocation space on
mapped memory. It also simplifies the relocation process.
- Move the start the module section next to the kernel. Remove the need for
-mcmodel=large on modules. Extends
2017 Oct 11
32
[PATCH v1 00/27] x86: PIE support and option to extend KASLR randomization
Changes:
- patch v1:
- Simplify ftrace implementation.
- Use gcc mstack-protector-guard-reg=%gs with PIE when possible.
- rfc v3:
- Use --emit-relocs instead of -pie to reduce dynamic relocation space on
mapped memory. It also simplifies the relocation process.
- Move the start the module section next to the kernel. Remove the need for
-mcmodel=large on modules. Extends
2010 Nov 11
0
[LLVMdev] named types with self-references
On Nov 11, 2010, at 8:45 AM, Jianzhou Zhao wrote:
> Hello,
>
> Can I define a named type ? %rt = {%rt}
> llvm-as can parse this definition without errors.
>
> JIT executes '%0 = alloca %rt' as allocating a memory with size 0.
> Because the llvm::TargetData::getTypeAllocSize accually returns 0 in
> this case. The function that calculates %rt's size is by the
2008 Nov 24
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
> The machines I worked with didn't support any integer ops, but GLSL
> let us get by with "emulated" 16 bit integers (storing and operating
> on them as floating point; divides required truncation after the op -
> that sort of thing).
Although my platform indeed supports integer operations, however, it
only supports integer +,-,*, not /. The document says if I need to
2010 Nov 11
2
[LLVMdev] named types with self-references
Hello,
Can I define a named type ? %rt = {%rt}
llvm-as can parse this definition without errors.
JIT executes '%0 = alloca %rt' as allocating a memory with size 0.
Because the llvm::TargetData::getTypeAllocSize accually returns 0 in
this case. The function that calculates %rt's size is by the
TargetData::getStructLayout, which calculates the a layout of %rt. It
can only returns 0
2006 Jul 10
1
Unexpected difference in Bounding Box of PDF graphics between (PR#9072)
huber at ebi.ac.uk wrote:
> Full_Name: Wolfgang Huber
> Version: R version 2.4.0 Under development (unstable) (2006-07-09 r38523)
> OS: i686-pc-linux-gnu
> Submission from: (NULL) (62.253.128.15)
>
>
> There appears to be unintentional behaviour in the size of the bounding box for
> PDF graphics produced with the current R2.4, compared to 2.3.1. I posted two PDF
>