Displaying 20 results from an estimated 1000 matches similar to: "Working with "ts" objects"
2007 Nov 28
2
extracting year an month from ts data set
I have an ascii data set of monthly observation starting in Jan 1946 with a
header.
hstarts
57
65
95
103
103
97
94
.
.
.
Which I read with the following code
tab6.1<-ts(read.table(fname, header=TRUE),frequency=12,start=c(1946,1))
I would like to run a time series model with dummy variables for each month.
If I had a variable which take values from 1 to 12 indicating the month I
could use
2012 Sep 28
1
blank plot----how do I make symbols appear
Hi,
I am trying to create a scatterplot, coding each point to one of 5
populations. I was successful when I did this for one set of data, yet
when I try plotting other data a blank plot appears (although the axes are
labelled and I can fit the regression lines from each population). I have
tried a variety of things to fix this but nothing seems to work.
I can plot the points if I do not
2014 Aug 15
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
Hi,
I have a problem regarding sub-register definitions and LiveIntervals on
our target. When a subregister is defined, other parts of the register
are always left untouched - they are neither read or def:ed.
It however seems that Codegen treats subregister definitions as somehow
clobbering the whole register.
The SSA-code looks like this after isel:
(Reg0 and Reg1 are 16bit registers. Reg2,
2014 Jun 08
2
[LLVMdev] [llvm] r210424 - Revert "Do materialize for floating point"
Why are you reverting patches for any area that you have no
authorization for ?
No build was broken. This patch is fine.
I am authorized to check in to the Mips area and Daniel is the
maintainer for that area.
On 06/08/2014 02:13 AM, Alp Toker wrote:
> Author: alp
> Date: Sun Jun 8 04:13:42 2014
> New Revision: 210424
>
> URL:
2009 Jan 19
0
[LLVMdev] HazardRecognizer and RegisterAllocation
On Jan 19, 2009, at 9:17 AM, Patrick Boettcher wrote:
> Hi list,
>
> in our LLVM-based-project we are writing a backend for our
> processor. The
> architecture is a quite straight-forward RISC, but it does not have
> hardware interlocks, i.e. data hazards involving memory access must be
> resolved by the compiler, either by scheduling unrelated
> instructions or
>
2009 Jan 19
2
[LLVMdev] HazardRecognizer and RegisterAllocation
Hi list,
in our LLVM-based-project we are writing a backend for our processor. The
architecture is a quite straight-forward RISC, but it does not have
hardware interlocks, i.e. data hazards involving memory access must be
resolved by the compiler, either by scheduling unrelated instructions or
by inserting NOOPs into the load delay slots:
----
For example, code which looks like that:
load
2017 Feb 14
2
Ensuring chain dependencies with expansion to libcalls
Hi all,
Our target does not have native support for 64-bit integers, so we rely on
library calls for certain operations (like sdiv). We recently ran into a
problem where these operations that are expanded to library calls aren't
maintaining the proper ordering in relation to other chains in the DAG.
The following snippet of a DAG demonstrates the problem.
t0: ch = EntryToken
t2:
2008 Aug 13
2
which alternative tests instead of AIC/BIC for choosing models
Dear R Users,
I am looking for an alternative to AIC or BIC to choose model parameters.
This is somewhat of a general statistics question, but I ask it in this
forum as I am looking for a R solution.
Suppose I have one dependent variable, y, and two independent variables,
x1 an x2.
I can perform three regressions:
reg1: y~x1
reg2: y~x2
reg3: y~x1+x2
The AIC of reg1 is 2000, reg2 is
2017 Sep 14
2
Live Register Spilling
> On Sep 13, 2017, at 9:03 PM, jin chuan see via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Hi All,
>
> Thanks for the reply. I managed to identify and fixed a few errors in my implementation.
>
> However, there are a few errors that i am not sure what is it indicating.
> For starters, i think i should explain what i am trying to achieve.
>
> I am
2016 May 09
2
Replacing an instruction in a post-RA pass
I'm writing a pass that looks at the operands of certain non-commutable
instructions and swaps a couple of them if certain conditions exist (a
register bank conflict in the instruction). If the conflict exists, I build
a new instruction which has the 2nd and 3rd operands swapped (using
BuildMI). Then I want to get rid of the original instruction. I had done
some searching and found that
2009 Jan 19
3
[LLVMdev] HazardRecognizer and RegisterAllocation
Hi Evan,
thanks for your response.
On Mon, 19 Jan 2009, Evan Cheng wrote:
>> For example, code which looks like that:
>>
>> load 0x1234, reg1
>> noop
>> noop
>> add reg1, 1
>> load 0x1236, reg2
>>
>> can be safely transformed to:
>>
>> load 0x1234, reg1
>> load 0x1236, reg2
>> noop
>> add reg1, 1
>>
>
2017 Feb 02
3
Register allocator behaves differently when compiling with and without -g
Hi all,
In several of our tests, I have noticed that the register allocator
allocates to virtual registers in a different order when compiling with the
clang option -g. Before entering the register allocator, the code is
identical when compiling with and without -g (with the exception of "
DBG_VALUE" instructions). The only difference I can see is the value
assigned to the slot index
2014 Jan 28
2
[LLVMdev] Load Instruction that changes value of two registers
Hello,
I'm writing a backend for an architecture that only has LOAD Instructions
that first copy the old value of the target register in another register
and after that load the provided value into the register.
Example of an addition:
load a, reg1; // -> copies old value of reg1 in reg2 and loads value from a
into reg1
load b, reg1; // -> copies old value of reg1 in reg2 and loads
2013 Feb 26
1
problem with nested loops
Each of the data sets contains monthly observations on price indices for 7 countries. I use the fitted values from reg1 in the reg2 model. The interior loop executes without error as long as I explicitly specify the data set, i.e. data=dat70. However the code fails to execute if I specify the model in the form of the commented line, i. e reg1 <-dynlm(form1,data=Dnames[j])
I get the following
2013 May 20
1
Objects created by more than one data call?
Hello, All:
If I use LazyData with the Ecdat package on R-Forge, "R CMD
check" reports "no visible binding for global variable
'nonEnglishNames'", where 'nonEnglishNames' is a dataset in Ecdat used
as the default argument for a function. With LazyData, that NOTE
disappears. However, then I get, "Warning: objects 'Hstarts',
2017 Feb 02
2
Register allocator behaves differently when compiling with and without -g
> On Feb 2, 2017, at 8:20 AM, David Blaikie <dblaikie at gmail.com> wrote:
>
> The goal/intent is that debug info does not affect code generation. There are (many?) bugs. I think Apple folks (cc'd Adrian) may be looking at this a bit recently, not sure.
>
> The fixes aren't usually too invasive (usually involve something counting instructions where it needs to skip
2017 Feb 02
2
Register allocator behaves differently when compiling with and without -g
> On Feb 2, 2017, at 8:20 AM, David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> The goal/intent is that debug info does not affect code generation. There are (many?) bugs. I think Apple folks (cc'd Adrian) may be looking at this a bit recently, not sure.
>
> The fixes aren't usually too invasive (usually involve something counting instructions where
2019 Mar 07
5
Writing unit tests - how to test re-orderable blocks...
We have a test that looks like this…
define void @array16_store() {
; CHECK-LABEL: array16_store:
; CHECK: ldi [[REG1:r[0-9]+]], 204
; CHECK: ldi [[REG2:r[0-9]+]], 170
; CHECK: sts int.array+3, [[REG2]]
; CHECK: sts int.array+2, [[REG1]]
; CHECK: ldi [[REG1:r[0-9]+]], 187
; CHECK: ldi [[REG2:r[0-9]+]], 170
; CHECK: sts int.array+1, [[REG2]]
; CHECK: sts int.array, [[REG1]]
; CHECK: ldi
2010 Feb 15
2
creating functions question
Hi All,
I am interested in creating a function that will take x number of lm
objects and automate the comparison of each model (using anova). Here
is a simple example (the actual function will involve more than what
Im presenting but is irrelevant for the example):
# sample data:
id<-rep(1:20)
n<-c(10,20,13,22,28,12,12,36,19,12,36,75,33,121,37,14,40,16,14,20)
2019 Mar 08
2
Writing unit tests - how to test re-orderable blocks...
I’m not sure if it’s truly deterministic. It always gives the same results (so far) on my machine but I’m not sure that’s enough.
My guess is it’s probably going to be deterministic on one machine but might well not be deterministic across environments. Like it might give varying results if cross compiled on different hosts, macOS vs intel Linux vs arm vs s390. (Obviously AVR is always a cross