similar to: Effect size in mixed models

All, If we can speculatively execute a load instruction, why isn’t it safe to hoist it out by promoting it to a scalar in LICM pass? There is a comment in LICM pass that if a load/store is conditional then it is not safe because it would break the LLVM concurrency model (See commit 73bfa4a). It has an IR test for checking this in test/Transforms/LICM/scalar-promote-memmodel.ll However, I have

I think gcc is right. It inserted a branch for n == 0 (the cbz at the top), so that's not a problem. In all other regards, this is safe: if you examine the sequence of loads and stores, it eliminated all but the first load and all but the last store. How's that unsafe? If I had to guess, the bug here is that LLVM doesn't want to hoist the load over the condition (which it is right

Hello, Rlisters I have to compute p-values that are on the tail of the distribution, P-values < 10^-20. However, my current implementations enable one to estimate P-values up to 10^-12, or so. A typical example is found below, where t is my critical value. ########### example - code adapted from Rassoc ####################### rho01 = 0.5 rho105 = 0.5 rho005 = 0.5 t = 8 z = 2

Thanks for the background on the concurrent memory model. So, is it sufficient that the loop entry is guarded by condition (cbz at top) for preventing the race? The loop entry will be guarded by condition if loop has been rotated by loop rotate pass. Since LICM runs after loop rotate, we can use ScalarEvolution::isLoopEntryGuardedByCond to check if we can speculatively execute load without

Hi all, I'm working on a target whose registers have equal-sized subregisters and all of those subregisters can be named (or the other way round: registers can be grouped into super registers). So for instance we've got 16 registers W (as in wide) W0..W15 and 32 registers N (as in narrow) N0..N31. This way, W0 is made by grouping N0 and N1, W1 is N2 and N3, W2 is N4 and N5, ..., W15 is

Hi llvmdev! I've been working on adding coroutines to LLVM. Mentioned below is the implementation plan I'm following, for suggestions, flames and other input. Using segmented stacks is a prerequisite. The idea is to associate every coroutine with a coroutine descriptor. A coroutine descriptor consists of four words: w0, w1, w2 and w3. w0 always contains the _launcher_, and invoking a

Add OSCCA SM3 secure hash algorithm (OSCCA GM/T 0004-2012 SM3). --- Makefile.in | 2 +- configure.ac | 2 +- digest-libc.c | 11 ++ digest-openssl.c | 1 + digest.h | 3 +- mac.c | 1 + sm3.c | 320 +++++++++++++++++++++++++++++++++++++++++++++++ sm3.h | 51 ++++++++ 8 files changed, 388 insertions(+), 3 deletions(-) create mode

Hi all, The last e-mails about beginners gave me the courage to post a question; from a beginner's perspective, there are a lot of questions that I'm tempted to ask. But I'm trying to find the answers either in the documentation, either in the about 15 free books I have, either in the help archives (I often found many similar questions posted in the past). Being an (still actual)

what about the memory address of e and f? can i get them? Thank you and best, Mo On Fri, Mar 10, 2017 at 5:02 PM, Tim Northover <t.p.northover at gmail.com> wrote: > On 10 March 2017 at 15:49, Mohammad Norouzi <mnmomn at gmail.com> wrote: > > for (auto& A : cast<CallInst>(BI)->arg_operands()) > > errs() << "--- " << A->getName()

On CentOS5 with the latest updates applied, the logwatch filter for postfix returns way too many lines from the log. I get an "unmatched entries" message and all messages that have gone through the system is listed. Here is an example: 8F930A8092: to=<morten at foo.bar>, orig_to=<morten at localhost>, relay=local, delay=0.19, delays=0.06/0.01/0/0.12, dsn=2.0.0,

Ping From: Mandeep Singh Grang [mailto:mgrang at codeaurora.org] Sent: Tuesday, February 03, 2015 4:34 PM To: 'llvmdev at cs.uiuc.edu' Cc: 'ghoflehner at apple.com'; 'apazos at codeaurora.org'; mgrang at codeaurora.org Subject: Question on Machine Combiner Pass Hi, In the file lib/CodeGen/MachineCombiner.cpp I see that in the function

Currently the AtomicExpandPass will lower the following IR: define i1 @foo(i32* %obj, i32 %old, i32 %new) { entry: %v0 = cmpxchg weak volatile i32* %obj, i32 %old, i32 %new _*release acquire*_ %v1 = extractvalue { i32, i1 } %v0, 1 ret i1 %v1 } to the equivalent of the following on AArch64: _*ldxr w8, [x0]*_ cmp w8, w1 b.ne .LBB0_3 // BB#1:

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.

Hi, I have just installed R 2.4.0 and when I try to load SpareseM, I get the following error message library(SparseM) Package SparseM (0.71) loaded. To cite, see citation("SparseM") Error in loadNamespace(package, c(which.lib.loc, lib.loc), keep.source = keep.source) : in 'SparseM' methods specified for export, but none defined: as.matrix.csr, as.matrix.csc,

The following patches shave some rough edges off the tools build system to allow cross compiling for at least arm32 and arm64 based on the Debian/Ubuntu multiarch infrastructure. They also add the necessary fixes to build for arm64 (which I have only tried cross, not native). I have posted some instructions on how to compile with these patches on the wiki:

First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I

As you may have noticed, we released a 64b S4 chip that runs an ILP32 variant of the AArch64 ABI, and now we'd like to upstream that work. I've pushed preliminary patches to https://github.com/TNorthover/llvm-project/pull/1/commits (arm64_32 branch in that repo) to accompany this RFC. The changes divide fairly neatly into three categories. First, there's AArch64 ILP32 support, which

Greetings from Rio de Janeiro, Brazil. I am looking for advice / references on binary logistic regression with weighted least squares (using lrm & weights), on the following context: 1) unbalanced sample (n0=10000, n1=700); 2) sampling weights used to rebalance the sample (w0=1, w1=14.29); e 3) after modelling, adjust the intercept in order to reflect the expected % of 1?s in the population

Dear R Users, I am trying to obtain a best-fit analytic distribution for a dataset with 11535459 entries. The data range in value from 1 to 300000000. I use: fitdistr(data, "gamma") to obtain mle's for the parameters. I get the following error: Error in optim(start, mylogfn, x = x, hessian = TRUE, ...) : non-finite finite-difference value [1] And the following warnings:

Oh yes. The "load package" under the "packages menu" in the Windows version does that. To check I typed "library(assist)" after starting R. Same behavior, ssr is found, but others like predict.ssr, and plot.ssr, give a "not found" message. Thanks for the suggestion. Mike