similar to: comparision and removal

Dear All, I have some problem in R which I'm explaining using an example: x<-(120,235,172,95,175,200,233,142) i want to remove the elements which are lesser than 100 and as a result i want two vectors y<-(containing elements <100) z<-(remaining elements) Moreover if I wish to use two different programs for vectors y and z. which command shall I use(will IF-ELSE work ?)

Dear R users, I am using a loop that does matrix multiplication in a manner (A%*%B)%*%(A) Here A is a row of data frame D of order(200x4). B is a (4x4). No need to say D[j,] is 1x4 so I am using for(j in seq(0.1,20,by=0.1)){ S&lt;- (D[j,]%*%B)%*%(D[j,]) print(S) } As a result I am geting only one value of S, which comes using j=20. I need all 200 values of S so

Dear All, I have to use loop over an array so I am using following procedure count<-1 repeat{ count<-count + 1 c(g[count],1:i[count]) ->qw if(count>5)break } as a result qw is [1] 0.9643836 1.0000000 2.0000000 3.0000000 4.0000000 5.0000000 [7] 6.0000000 7.0000000 8.0000000 9.0000000 10.0000000 11.0000000 [13] 12.0000000 13.0000000 14.0000000 15.0000000 16.0000000

Hi Mon Ping, > If I remember correctly, I was also not fond of passing another > TargetAddrSpace reference to the TargetData object. I was hoping that we > could encode the information as a target description string like we do for > ABI information. I just don't want to end up with too many objects that > describe the machine. One can argue that we shouldn't pollute

On Mon, Mar 10, 2014 at 3:59 PM, Olly Betts <olly at survex.com> wrote: > Exactly what approach the project takes isn't nailed down - it just > seemed something which would be interesting for a student to work on, > and would be useful to Xapian users. > > My understanding of the current clustering branch (which may not be > completely accurate) is that it clusters

Hi all, I've been a tad busy in the last few weeks, but I don't think this issue is settled yet. > > the relations between each address space (equivalent, disjoint, subset/ > > superset). > > Any thoughts on that? Should they also belong in TargetData? > Only if absolutely required, see below. Is there any other place they would fit in better? What piece of below

On Mar 24, 2011, at 5:42 PM, Borja Ferrer wrote: > The last copy instruction should be removed as pointed out above, but since R27R26 is killed in the load instruction it has to be emitted. About the insane amount of regclasses there, the load/store and the andi instructions take subsets of regs from the main register class, they cant work with all registers, that's why STW and LDW needs

On Fri, Jul 12, 2013 at 3:49 PM, Shuxin Yang <shuxin.llvm at gmail.com> wrote: > 3. How to parallelize post-IPO stage > ==================================== > > From 5k' high, the concept is very simple, just to > step 1).divide the merged IR into small pieces, > step 2).and compile each of this pieces independendly. > step 3) the objects of each piece

Hi Mon Ping, > I don't have a problem having another class, TargetAddrSpace, to store this > information. However, I don't think it make sense being a standalone pass. > Address spaces seems to part of the TargetData and it seems more natural > to ask the TargetData to return the TargetAddrSpace object (similar to > struct layout) to describe the relationships

Attention R users, especially those that are experienced enough to be opinionated, I need your input. Consider the following simple plot: x <- rnorm(100) y <- rnorm(100) plot(x, y, bty='n') A colleague (and dreaded SAS user) commented that she thought that my plots could be "cleaned up" by connecting the X and Y axes. I know that I can do that with bty='l' but I

Hi Matthew, > I'm investigating a problem with "Machine Instruction Scheduling" that is rooted > in incorrect alias information. > > Things go wrong in the "Merge disjoint stack slots"[1] pass when a store > instruction fails to get updated after its stack slot is merged. As a result, > when "Machine Instruction Scheduling" runs, it incorrectly

Hello all. I'm investigating a problem with "Machine Instruction Scheduling" that is rooted in incorrect alias information. Things go wrong in the "Merge disjoint stack slots"[1] pass when a store instruction fails to get updated after its stack slot is merged. As a result, when "Machine Instruction Scheduling" runs, it incorrectly re-orders the store and a

On 7/17/13 12:35 PM, Diego Novillo wrote: > On Fri, Jul 12, 2013 at 3:49 PM, Shuxin Yang <shuxin.llvm at gmail.com> wrote: > >> 3. How to parallelize post-IPO stage >> ==================================== >> >> From 5k' high, the concept is very simple, just to >> step 1).divide the merged IR into small pieces, >> step 2).and compile

So, you can't have disjoint sets, and have one of set that says "i access everything". Because it would contain everything :) Thus, I assume by your description you meant "we want to maintain multiple disjoint partitions of the same set of accesses" (which is not quite the same as just having one special partition). When one partition is a refinement of the other (as

Hi Matthijs, Sorry for not responding earlier. I have a few comments. On Aug 7, 2008, at 7:41 AM, Matthijs Kooijman wrote: > Hi Mon Ping, > > I've again attached a patch, wich lets LLVM know about about the > relations > between different address spaces. Instead of cramming this info in > with > TargetData (with all kinds of unwanted side effects, especially for

Hi Mon Ping, I've again attached a patch, wich lets LLVM know about about the relations between different address spaces. Instead of cramming this info in with TargetData (with all kinds of unwanted side effects, especially for the IR), I opted to create a new pass, TargetAddrspaces, which holds this information. Just like TargetData, this can be added to the passmanager by the tool running

Hi Matthijs, > >>> Specifically, I would like instcombining to be able to use this >>> info to >>> remove useless bitcasts. Also, this information is useful for >>> clang to >>> know when inserting an implicit cast makes sense and when it >>> would be an >>> error. >> Clang should just reject implicit casts in *any*

Hello Jakob, thanks for the reply. The three regclasses involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean: DREGS: R31R30, R29R28 down to R1R0 (16 regs) DLDREGS: R31R30, R29R28 down to R17R16 (8 regs) PTRREGS: R31R30, R29R28, R27R26 (3 regs) All classes intersect each other

On 08/11/2013 08:41 AM, Micah Villmow wrote: > How about this as a solution. > > Add one hook into TargetInstrInfo, and one into TargetISelLowering. > > 1) getAddressSpaceRelation(unsigned AS1, unsigned AS2) - Returns either disjoint, subset, superset, equal. Function defaults to equal. > 2) isAddressSpaceSupported(unsigned AS) - Returns true if supported, false otherwise.

On Jul 22, 2008, at 1:36 AM, Matthijs Kooijman wrote: >> Yep, I think it makes sense for TargetData to have info about the >> size/ >> alignment of a pointer in each addr space. That is also easy to >> encode. > Which is an added bonus, but the original subject under discussion > was the > relations between each address space (equivalent, disjoint, subset/