similar to: Help with "non-integer #successes in a binomial glm"

I got the following warning messages when I did a binomial logit regression using glm(): Warning messages: 1: Algorithm did not converge in: glm.fit(x = X, y = Y, weights = weights, start = start, etastart = etastart, 2: fitted probabilities numerically 0 or 1 occurred in: glm.fit(x = X, y = Y, weights = weights, start = start, etastart = etastart, Can some one share your thoughts on how to

Dear list, I try to update the prabclus package. R CMD check works nicely, no warnings, good results in all tests. However, building the package fails: ginkgo:/disk5/home/chrish/RAusw/libsrc R CMD build prabclus * checking for file 'prabclus/DESCRIPTION' ... OK * preparing 'prabclus': * checking whether 'INDEX' is up-to-date ... OK * removing junk files * building

I'm pretty new to R and would appreciate some help interpreting the output of a function that was recommended to me. I've used the *envfit *function in the vegan package to plot vectors of four climate variables onto a species matrix ordination. The output indicates that only a single variable (mean_temp) is significant: ***VECTORS NMDS1 NMDS2 r2

Hi, the following Code demonstrates an possibly Error in R (or you can explain me, why this happens, thanks in advance) Code: ##################################### testClass <- function( stackData= c()) { list( write= function( ...) { sChain= "" for( s in c( stackData, ...)) { sChain= paste( sChain, '"', sub( '"',

Hi there, Quoting RFC 3501 sec. 7.4.2 ?FETCH Response? (data item BODYSTRUCTURE): ?A body type of type MESSAGE and subtype RFC822 contains, immediately after the basic fields, the envelope structure, body structure, and size in text lines of the encapsulated message.? According the ABNF (RFC 3501 sec. 9) the envelope structure is that of the ENVELOPE FETCH data item, and the

Hi, Assume I define registers R0...R15 and two register classes RegA and RegB. RegA contains R0 to R7 while RegB contains R0 to R15. Then I check the machine instruction, it seems that in some cases, the %vreg0 belongs to RegB; in other cases %vreg1 belongs to RegA_RegB. Can you tell me how TableGen decides which is which? At first, I guess &verg0 will be assigned by R8 to R15 only so that

Hi, I'm trying to complete the lowering for a new microcontroller. I'm using LLVM 3.8. For now this lowering crashes on 'Store' node, which is actually not yet defined. I've tried to map the ISel 'Store' node to architecture specific instructions. I've define the following semantic to my architecture specific instructions: def MOVSUTO_SU_rr :

Hi, It seems to me that the TwoAddressInstructionPass::runOnMachineFunction method has some problems when the tied destination register has a subReg. The two changes below improves the situation for me but I'm all new to this so I'm not sure how it's supposed to work. I'm running on 2.9. Any comments? @@ -1172,12 +1172,20 @@ bool

Hi, I'm new to asterisk and have a little trouble in developing my first more complex dialplan. The basic task is a click to call solution: - call one number via sip, play some announcements, do cdr etc. and put the callee into an conference room with music on hold - call a second number via sip, play some announcements, do cdr etc. put the callee into the same conference - have a nice chat

Dear contributors: I have vector A composed of numbers wich have values equal to 1 and different to 1. I want to transform de components with a value=1 to a component of value=0, and those with a value different to1, to a value=1. Then I want to take out the components=0. Thanks in advance, Juan Pablo [[alternative HTML version deleted]]

Hi all. I'm looking for an advice on how to deal with inefficient code generation for Intel Nehalem/Westmere architecture on 64-bit platform for the attached test.cpp (LLVM IR is in test.cpp.ll). The inner loop has 11 iterations and eventually unrolled. Test.lea.s is the assembly code of the outer loop. It simply has 11 loads, 11 FP add, 11 FP mull, 1 FP store and lea+mov for index

> > Thank you Chris. I will try to implement the TwoAddress pass to run on > > machine code. Why it has not been originally implemented to run on > > machine code? > > I'm not sure what you mean. It definitely does run on machine code. I was thinking that it only transformed instructions with virtual registers because of this code in the TwoAddressInstructionPass.cpp:

This sounds like llvm.org/pr13320. On 17 September 2013 18:20, Bader, Aleksey A <aleksey.a.bader at intel.com> wrote: > Hi all. > > > > I’m looking for an advice on how to deal with inefficient code generation > for Intel Nehalem/Westmere architecture on 64-bit platform for the attached > test.cpp (LLVM IR is in test.cpp.ll). > > The inner loop has 11 iterations

HI I am trying to analyse data which is left-censored (i.e. has values below the detection limit). I have been using the NADA package of R to derive summary statistics and do some regression. I am now trying to carry out regression on paired data where both my X and Y have left-censored data within them. I have tried various commands in R: rega = cenreg(Cen(conc, cens_ind) ~ Gp_ident))? with

Hi, Thx for your help... Here is the IR code: ; ModuleID = 'foo_bar.c' target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @.str = private unnamed_addr constant [6 x i8] c"MAIN\0A\00", align 1 ; Function Attrs: nounwind uwtable define i32 @main(i32 %argc, i8** %argv) #0 { entry: %retval = alloca i32,

The two address pass is only concerned about register pressure. It sounds like it should be taught about profitability. In cases where profitability can only be determined with something machinetracemetric then it probably should live it to more sophisticated pass like regalloc. In this case, we probably need a profitability target hook which knows about lea. We should also consider disabling

Hi, I'm having trouble using virtual register in the X86 backend. I implemented a new intrinsic and I use a custom inserter. The goal of the intrinsic is to set the content of the stack to zero at the end of each function. Here is my code: MachineBasicBlock * X86TargetLowering::EmitBURNSTACKWithCustomInserter( MachineInstr *MI, MachineBasicBlock

>-----Original Message----- >From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of >Sanjoy Das via llvm-dev >Sent: Thursday, December 03, 2015 11:16 PM >To: Quentin Colombet <qcolombet at apple.com> >Cc: llvm-dev at lists.llvm.org >Subject: Re: [llvm-dev] analyzePhysReg question > >I think this is related to PR25033:

Dear all: I have found a big bug on xen concerning time virtualization. Please let me show you the whole process: 1 Phenomenon when I run a JVM based program in IE browser in my Virtual Machine, I have found clearly that time at the right bottom corner in my VM gets more slower and slower. I studied the bug deeply, and found something below. 2 Xen vmx_vmexit_handler --> ......... -->

On Oct 2, 2013, at 11:48 PM, Evan Cheng <evan.cheng at apple.com> wrote: > The two address pass is only concerned about register pressure. It sounds like it should be taught about profitability. In cases where profitability can only be determined with something machinetracemetric then it probably should live it to more sophisticated pass like regalloc. > > In this case, we