similar to: error in solve_technical question

Displaying 20 results from an estimated 1000 matches similar to: "error in solve_technical question"

2005 Mar 01
2
part of name to Date
hi everybody, i try to extract a part of name to a date : like : "VGT1_VGT2_CONTR_B020030401.H0V0.MIR" to "20030401" but the beginning of the files changes i have a list of files: [,1] [1,] "VGT1_CONTR_B020020301.H0V0.MIR" [2,] "VGT1_VGT2_CONTR_B020020611.H0V0.MIR" [3,]
2005 Mar 07
1
simple problem
Hello, I have a little problem, very simple, but i can't solve it. I have a list of files I have a function I want that the function take files one to one (the results is a matrix (1 file (the values) for 1 column)) I used some functions (like apply, lapply and more) but in each case, i have a warning message : "only first element of `description' argument used " it takes
2013 Jun 28
3
[LLVMdev] Question regarding the x86 SBB instruction.
Hi, I have the x86 SBB instruction. how should I represent this in LLVM IR. (as part of a decompiler from binary to LLVM IR) Pre-conditions: %eax = 0xffffffff %edx = 0xffffffff %carry = 1 SBB %eax, %edx // %edx is the destination doing %edx = %edx - (%eax + carry) JC jump_destination1 // If the Carry flag is set, jump to jump_destination1 How do I represent this correctly in LLVM
2013 Jun 28
0
[LLVMdev] Question regarding the x86 SBB instruction.
Look at the __builtin_addc* builtins in clang. I am currently working on an optimization which transforms said intrinsics into chains of ADCs/SBBs. Michael On Jun 28, 2013, at 5:51 AM, James Courtier-Dutton <james.dutton at gmail.com> wrote: > Hi, > > I have the x86 SBB instruction. how should I represent this in LLVM > IR. (as part of a decompiler from binary to LLVM IR)
2013 Mar 12
6
[LLVMdev] help decompiling x86 ASM to LLVM IR
Hi, I am looking to decompile x86 ASM to LLVM IR. The original C is this: int test61 ( unsigned value ) { int ret; if (value < 1) ret = 0x40; else ret = 0x61; return ret; } It compiles with GCC -O2 to (rather cleverly removing any branches): 0000000000000000 <test61>: 0: 83 ff 01 cmp $0x1,%edi 3:
2013 Mar 12
0
[LLVMdev] help decompiling x86 ASM to LLVM IR
James Courtier-Dutton <james.dutton at gmail.com> writes: > I am looking to decompile x86 ASM to LLVM IR. > The original C is this: > int test61 ( unsigned value ) { > int ret; > if (value < 1) > ret = 0x40; > else > ret = 0x61; > return ret; > } > > It compiles with GCC -O2 to (rather
2018 Nov 27
2
Rather poor code optimisation of current clang/LLVM targeting Intel x86 (both -64 and -32)
"Sanjay Patel" <spatel at rotateright.com> wrote: > IIUC, you want to use x86-specific bit-hacks (sbb masking) in cases like > this: > unsigned int foo(unsigned int crc) { > if (crc & 0x80000000) > crc <<= 1, crc ^= 0xEDB88320; > else > crc <<= 1; > return crc; > } To document this for x86 too: rewrite the function
2019 Mar 04
2
Where's the optimiser gone (part 11): use the proper instruction for sign extension
Compile with -O3 -m32 (see <https://godbolt.org/z/yCpBpM>): long lsign(long x) { return (x > 0) - (x < 0); } long long llsign(long long x) { return (x > 0) - (x < 0); } While the code generated for the "long" version of this function is quite OK, the code for the "long long" version misses an obvious optimisation: lsign: # @lsign mov
2018 Nov 06
4
Rather poor code optimisation of current clang/LLVM targeting Intel x86 (both -64 and -32)
Hi @ll, while clang/LLVM recognizes common bit-twiddling idioms/expressions like unsigned int rotate(unsigned int x, unsigned int n) { return (x << n) | (x >> (32 - n)); } and typically generates "rotate" machine instructions for this expression, it fails to recognize other also common bit-twiddling idioms/expressions. The standard IEEE CRC-32 for "big
2013 Jul 14
9
[LLVMdev] [PATCH] x86/asm: avoid mnemonics without type suffix
1c54d77 (x86: partial unification of asm-x86/bitops.h, 2008-01-30) changed a bunch of btrl/btsl instructions to btr/bts, with the following justification: The inline assembly for the bit operations has been changed to remove explicit sizing hints on the instructions, so the assembler will pick the appropriate instruction forms depending on the architecture and the context. Unfortunately,
2013 Jul 19
2
[LLVMdev] SIMD instructions and memory alignment on X86
Hmm, maybe sse isn't being enabled so its falling back to emulating sqrt? On Thu, Jul 18, 2013 at 10:45 PM, Peter Newman <peter at uformia.com> wrote: > In the disassembly, I'm seeing three cases of > call 76719BA1 > > I am assuming this is the sqrt function as this is the only function > called in the LLVM IR. > > The code at 76719BA1 is: > >
2013 Jul 19
0
[LLVMdev] SIMD instructions and memory alignment on X86
In the disassembly, I'm seeing three cases of call 76719BA1 I am assuming this is the sqrt function as this is the only function called in the LLVM IR. The code at 76719BA1 is: 76719BA1 push ebp 76719BA2 mov ebp,esp 76719BA4 sub esp,20h 76719BA7 and esp,0FFFFFFF0h 76719BAA fld st(0) 76719BAC fst dword ptr [esp+18h] 76719BB0 fistp
2010 Jun 11
4
[LLVMdev] Bignum development
Hi all, After searching for a decent compiler backend for ages (google sometimes isn't helpful), I recently stumbled upon LLVM. Woot!! I work on bignum arithmetic (I'm a professional mathematician) and have recently decided to switch from developing GPL'd bignum code to BSD licensed code. (See http://www.mpir.org/ which I contributed to for a while - a fork of GMP). Please bear with
2007 Jun 25
2
two channels, each dropping into the same context, different behavior.
So, incoming calls on zap work just as I expect them - an intro is played, the caller hits 1 for sale 2 for support or dials an extension. I'm using the privacy option for all extensions. When calls come in from zap, they caller is played the priv-recordintro recording, they say their name, and everything happens normally from there on out. However, when the call comes in from sip and
2013 Jul 19
0
[LLVMdev] SIMD instructions and memory alignment on X86
Is there something specifically required to enable SSE? If it's not detected as available (based from the target triple?) then I don't think we enable it specifically. Also it seems that it should handle converting to/from the vector types, although I can see it getting confused about needing to do that if it thinks SSE isn't available at all. On 19/07/2013 3:47 PM, Craig Topper
2014 May 13
2
[LLVMdev] Missed optimization opportunity in 3-way integer comparison case
While looking at what llvm writes for this testcase, I noticed that there is one redundant operation in resulting assembly. The second 'cmp' operation there is essentially identical to the first one, with reversed order of arguments. Therefore, it is not needed. This testcase is a simple integer comparison routine, similar to what qsort would take to sort an integer array. I think
2012 Nov 12
3
nomenclature for conf files
It might sound stupid, but I'd like to know if there's any difference. Are those 3 line the same? WITH_KMS=YES WITH_KMS="YES" WITH_KMS=yes Best regards Zoran
2010 May 20
3
samba and bind9 problem
I followed the manual and got 3 problems 1. When i start samba i got error: ../dsdb/dns/dns_update.c:249: Failed DNS update - NT_STATUS_IO_TIMEOUT 2. When i join some computer bind9 doesent update the host in DNS. 3. When i start command /usr/local/samba/sbin/samba_dnsupdate --verbose shell sometimes back result sometimes not.'' -- -- Pozdrav Aleksandar
2017 Oct 05
3
dealing with a messy dataset
dear Jim, Thanks for your reply and your proposition. I forgot to provide the header of the dataframe, here it is: ================================================================================ Byte-by-byte Description of file: lvg_table2.dat -------------------------------------------------------------------------------- Bytes Format Units Label Explanations
2010 Aug 24
4
OT: redhat training and RHES6
Greetings. I am planning on getting my RHCE in the near future. I thinking I should wait until 6 comes out before proceeding. That being said, I don't want to wait past the end of this year. That being said, do you all have any information about how long it takes for their training platform to catch up to their release? Which is to say, if RHES 6 is released on day 1, at what point