Displaying 20 results from an estimated 11000 matches similar to: "Multiple comparisons: its a trap!"
2010 Oct 01
2
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
On 1 Oct 2010, at 13:35, Bill Wendling wrote:
> On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote:
>
>> Bill Wendling wrote:
>>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>>>
>>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>>>
>>>>> Our architecture has 1-bit boolean predicate registers.
>>>>>
2010 Sep 29
2
[LLVMdev] comparison pattern trouble
Our architecture has 1-bit boolean predicate registers.
I've defined comparison
def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
But then I end up having the following bug:
Code
%0 = zext i8 %data to i32
%1 = zext i16 %crc to i32
%2 = xor i32 %1, %0
%3 = and i32 %2, 1
%4 =
2010 Sep 29
1
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
> Our architecture has 1-bit boolean predicate registers.
>
> I've defined comparison
>
>
> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>
>
>
>
> But then I end up having the following bug:
>
>
2008 Sep 12
3
[LLVMdev] Difficulty with reusing DAG nodes.
I'm trying to implement *MUL_LOHI for my processor.
My processor has mulxss (e.g.) that gives the 32 high bits of a 64 bit
multiply.
I tried this in ios2ISelDAGToDAG.cpp:
/// Mul/Div with two results
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI: {
SDValue Op1 = Node->getOperand(0);
SDValue Op2 = Node->getOperand(1);
AddToISelQueue(Op1);
2010 Sep 29
0
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>
>> Our architecture has 1-bit boolean predicate registers.
>>
>> I've defined comparison
>>
>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
2013 Jul 16
0
[LLVMdev] [PATCH 2/2] X86: infer immediate forms of bit-test instructions
The instruction mnemonics for the immediate forms of bit-test
instructions including bt, btr and bts, btc do not work. llvm-mc barfs
with:
error: ambiguous instructions require an explicit suffix
This is highly user-unfriendly, since we can easily infer what the user
meant by inspecting $imm and translating the instruction appropriately.
Do it exactly as the Intel manual describes. Note that
2009 Sep 02
1
[LLVMdev] LangRef description of 'add nsw' doesn't match reality
The langref says for the 'add' instruction:
Syntax:
<result> = add <ty> <op1>, <op2> ; yields {ty}:result
<result> = nuw add <ty> <op1>, <op2> ; yields {ty}:result
<result> = nsw add <ty> <op1>, <op2> ; yields {ty}:result
<result> = nuw nsw add <ty> <op1>, <op2> ;
2013 Jan 09
0
[LLVMdev] Global variable initializer type does not match global variable type
Peter Zotov писал 09.01.2013 19:59:
> Hello.
>
> I've managed to create a bitcode file (attached; also available at
> [1]) which produces
> a series of identical errors when verified:
>
> | Global variable initializer type does not match global variable
> type!
> | %i.NilClass* @nil
>
> When ran through llvm-dis and recompiled, through, it verifies
>
2010 Oct 01
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote:
> Bill Wendling wrote:
>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>>
>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>>
>>>> Our architecture has 1-bit boolean predicate registers.
>>>>
>>>> I've defined comparison
>>>>
>>>> def
2017 Nov 29
3
RFC: Adding 'no-overflow' keyword to 'sdiv'\'udiv' instructions
Introduction:
We would like to add new keyword to 'sdiv'\'udiv' instructions i.e. 'no-overflow'.
This is the updated solution devised in the discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-October/118257.html
The proposed keywords:
"nof" stands for 'no-overflow'
Syntax:
<result> = sdiv nof <ty> <op1>,
2010 Sep 08
5
Newbie cross tabulation issue
hi, i'm new in R and i need some help. Please, ¿do you know a function how
can process cross tables for many variables and show the result in one table
who look like this?:
+----------------------------------------------------+
|------------------ | X variable |
|----------------- | Xop1 | Xop2 | Xop3|.....|
+----------------------------------------------------+
|Yvar1 |
2018 Feb 10
0
Optim function returning always initial value for parameter to be optimized
On 02/10/2018 06:00 AM, r-help-request at r-project.org wrote:
> Did you check the gradient? I don't think so. It's zero, so of course
> you end up where you start.
>
> Try
>
> data.input= data.frame(state1 = (1:500), state2 = (201:700) )
> err.th.scalar <- function(threshold, data){
>
> state1 <- data$state1
> state2 <- data$state2
>
2010 Sep 30
4
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
Bill Wendling wrote:
> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>
>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>
>>> Our architecture has 1-bit boolean predicate registers.
>>>
>>> I've defined comparison
>>>
>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set
2010 Oct 04
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG
Please test if r115571 has fixed it.
Evan
On Oct 4, 2010, at 5:00 AM, Heikki Kultala wrote:
> Bill Wendling wrote:
>> On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote:
>>
>>> Bill Wendling wrote:
>>>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>>>>
>>>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
2010 Oct 04
2
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG
Bill Wendling wrote:
> On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote:
>
>> Bill Wendling wrote:
>>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>>>
>>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>>>
>>>>> Our architecture has 1-bit boolean predicate registers.
>>>>>
>>>>> I've
2011 Apr 30
1
More flexible aggregate / eval
Dear list,
I would like to do some calculation using different grouping variables.
My 'df' looks like this:
# Some data
set.seed(345)
id <- seq(200,400, by=10)
ids <- sample(substr(id,1,1))
group1 <- rep(1:3, each=7)
group2 <- rep(1:2, c(10,11))
group3 <- rep(1:4, c(5,5,5,6))
df <- data.frame(id, ids, group1, group2, group3)
df <- rbind(df, df, df)
df$time <-
2018 Feb 09
1
Optim function returning always initial value for parameter to be optimized
Hello,
I'm trying to fminimize the following problem:
You have a data frame with 2 columns.
data.input= data.frame(state1 = (1:500), state2 = (201:700) )
with data that partially overlap in terms of values.
I want to minimize the assessment error of each state by using this function:
err.th.scalar <- function(threshold, data){
state1 <- data$state1
state2 <- data$state2
2009 Feb 19
1
[LLVMdev] help: about how to use tblgen to constraint operand.
I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr.
But I need to use an even/odd register pair to save its 2 operands.
I define in mytarget.td:
myfmdrr:
SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;
def my_fmdrr : ...........
def myFMDRR : ....
(outs FPR: $result), ins(GPR:
2011 Dec 02
0
[LLVMdev] RFC: Machine Instruction Bundle
. and yes, one more thing. On some architectures it might be desirable to
know the _order_ of instructions in the packet. That is a bit trickier..
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Evan Cheng
Sent: Friday, December 02, 2011 2:40 PM
To: LLVM Dev
Subject: [LLVMdev]
2008 Aug 28
1
[LLVMdev] instruction CE_GEP
Hi all,
I have a question with the "getelemptr" instruction.
E.g.: I have some GEP instructions in my program.
Some look like:
<INST_GEP op0=26 op1=64 op2=429/>
.
<INST_GEP op0=341 op1=64 op2=101 op3=499 op4=0/>
The first instruction above in assembly file:
%tmp60 = getelementptr [512 x i32]* @weights, i32 0, i32 %k.3.ph
Ok, we see it all:
Index of @weights in value