Displaying 20 results from an estimated 800 matches similar to: "predict assistance"
2016 Nov 03
2
rotl: undocumented LLVM instruction?
Is there any way to get it to delay this optimization where it goes from
this:
Initial selection DAG: BB#0 'bclr64:entry'
SelectionDAG has 14 nodes:
t0: ch = EntryToken
t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1
t6: i64 = sub t4, Constant:i64<1>
t7: i64 = shl Constant:i64<1>, t6
2016 Nov 03
3
rotl: undocumented LLVM instruction?
Setting the ISD::ROTL to Expand doesn't work? (via SetOperation)
You could also do a Custom hook if that's what you're looking for.
On Thu, Nov 3, 2016 at 5:12 PM, Phil Tomson <phil.a.tomson at gmail.com> wrote:
> ... or perhaps to rephrase:
>
> In 3.9 it seems to be doing a smaller combine much sooner, whereas in 3.6
> it deferred that till later in the
2016 Nov 03
2
rotl: undocumented LLVM instruction?
One option may be to prevent the formation of ROTL, if possible, and
then generating rol by hand.
Marking it as "expand" would likely stop the DAG combiner from creating
it. Then you could "preprocess" the selection DAG before the instruction
selection and do the pattern matching yourself.
-Krzysztof
On 11/3/2016 4:24 PM, Phil Tomson via llvm-dev wrote:
> I could try
2016 Nov 02
3
rotl: undocumented LLVM instruction?
We've recently moved our project from LLVM 3.6 to LLVM 3.9. I noticed one
of our code generation tests is breaking in 3.9.
The test is:
; RUN: llc < %s -march=xstg | FileCheck %s
define i64 @bclr64(i64 %a, i64 %b) nounwind readnone {
entry:
; CHECK: bclr r1, r0, r1, 64
%sub = sub i64 %b, 1
%shl = shl i64 1, %sub
%xor = xor i64 %shl, -1
%and = and i64 %a, %xor
ret i64
2024 Jan 29
1
linear programming in R | limits to what it can do, or my mistake?
Question for 'experts' in LP using R (using the lpSolve package, say) --
which does not apply to me for the sort of problem I describe below.
I've run any number of LP's using lpSolve in R, but all of them to date
have objective and constraint functions that both contain the same
variables. This lets you set up a LHS and RHS matrix/vector that are
symmetrical.
But, for a
2009 Mar 18
1
Reading a file line by line - separating lines VS separating columns
Hello all.
I wish to read a large data set into R. My current issue is in getting the
data so that R would be able to access it. Using read.table won't work
since the data is over 1GB in size (and I am using windows XP), so my plan
was to read the file chunk by chunk and each time move it into bigmemory
(I'll play with that when the time will come, maybe ff is better ?!).
I encountered
2024 Jan 30
1
linear programming in R | limits to what it can do, or my mistake?
Apart from the fact that the statement "such that t1+t2+t3+t4=2970 (as
it must)" is not correct, the LP can be implemented as follows:
library(lpSolve)
LHS <- rbind(
c(0,0,0,0, 1, 0, 0,0),
c(1,0,0,0,-1, 1, 0,0),
c(0,1,0,0, 0,-1, 1,0),
c(0,0,1,0, 0, 0,-1,1),
cbind(-diag(4),diag(4)),
c(0,0,0,0,0,1,0,0),
c(0,0,0,0,0,0,1,0),
c(0,0,0,0,0,0,0,1)
)
RHS <-
2007 Nov 29
3
lustre osd implementation
hello,
does lustre support OSD T10 standard? Can it be used with IBM''s/Intel''s OSD
initiator and target?
Thanks,
Ashish
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2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
Hi,
I am having some issues with how some of the instructions are being
legalized.
So this is my intial basic block. The area of concern is the last three
instructions. I will pick and choose debug output to keep this small.
SelectionDAG has 36 nodes:
t0: ch = EntryToken
t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507
t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17
2010 Mar 10
1
PCA
Hello,
I am trying to complete a PCA on a set of standardized ring widths from 8
different sites (T10, T9, T8, T7, T6, T5, T3, and T2).
The following is a small portion of my data:
T10 T9 T8 T7 T6 T5 T3 T2 1.33738 0.92669 0.91146 0.98922 0.9308 0.88201
0.92287 0.91775 0.82181 1.05319 0.92908 0.97971 0.95165 0.98029 1.14048
0.77803 0.88294 0.96413 0.90893 0.87957 0.9961 0.74926 0.71394 0.70877
2017 Sep 21
1
VSelect Instruction Error
Hello,
I am getting this error. What instruction is required to be implemented?
LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16
t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>,
undef:i64
t659: i64 = FrameIndex<1>
t10: i64 = undef
t11: v32i32,ch = load<LD128[%sunkaddr45](align=4)(tbaa=<0x481f1e8>)> t0,
t8, undef:i64
2019 Feb 08
2
Unfolded additions of constants after promotion of @llvm.ctlz.i16 on SystemZ
Hi,
SystemZ supports @llvm.ctlz.i64() natively with a single instruction
(FLOGR), and lesser bitwidth versions of the intrinsic are promoted to i64.
For some reason, this leads to unfolded additions of constants as shown
below:
This function:
define i16 @fun(i16 %arg) {
%1 = tail call i16 @llvm.ctlz.i16(i16 %arg, i1 false)
ret i16 %1
}
,gives this optimized DAG as input to instruction
2010 Jan 12
1
parsing protocol of states
Dear R-users,
actually i try to parse some state protocols for my work. i an easy
stetting the code below works fine, if states are reached only once. in
harder settings it could be possible that one state gets visited more
times. in this case for me its interesting to see how much waiting time
lies between to states on the whole.
by the way i didn't use R as a parsing tool so far, so
2012 Aug 29
4
Sorting of columns of a matrix
Dear all,
Please suggest me how can I do it.
I have a matrix which look like following:
x1 x2 x3 t1 .01 0.3 0 t2 0 0.1 0.01 t3 0 .01 .01 t4 0 0 t5 5 0 0 t6
0 0 0 t7 0 0 0 t8 0 0 0 t9 0.6 0 0 t10 0 0 0.66 t11 0 0.6 0.11 t12 0
0.4 0
I want to sort decreasing order in each column based on rows. and then to
display only those rows which has a value. The expected out put matrix will
2003 Dec 10
1
How to remove extra spaces introduced (?) by write.table
Dear Group,
My question relates to the write.table function.
I have created a data.frame containing both "character" and "numeric" columns.
When I use the write.table function to write this table into a text file
spaces are added into the "numeric" columns so that the number of digits in
each column is the same. This extra space is added before the actual number.
2017 Jul 07
2
Error in v64i32 type in x86 backend
also i further run the following command;
llc -debug filer-knl_o3.ll
and its output is attached here. by looking at the output can we say that
legalization runs fine and the error is due to instruction selection/
pattern matching which is not yet implemented?
so do i need to worry and try to correct it at this stage or should i move
forward to implement instruction selection/ pattern matching?
2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
But isn't kinda silly that we transform to xor and then we transform it
back. What is the advantage in doing so? Also, since we do that method, I
now have to introduce setcc patterns for i1 values, instead of being able
to just use logical pattern operators like not.
-Dilan
On Fri, Jul 21, 2017 at 11:00 AM Dilan Manatunga <manatunga at gmail.com>
wrote:
> For some reason I
2011 Aug 13
1
Own R function doubt
Hi to all the people again,
I was writting a simply function in R, and wish to collect the results in a
excel file. The work goes as follows,
Ciervos<-function(K1, K0, A, R,M,Pi,Hembras)
{B<-(K1-K0)/A
T1<-(R*Pi*Hembras-M*Pi+B)/(Pi-M*Pi+R*Pi*Hembras)
P1<-Pi-B
R1<-P1*Hembras*R
M1<-P1*M
T2<-(R1-M1+B)/(P1-M1+R1)
P2<-P1-B
R2<-P2*Hembras*R
M2<-P2*M
2018 Jan 07
2
No answer from upsrw <ups name> command
2019 Jun 24
3
How to handle ISD::STORE when both operands are FrameIndex?
Hello.
After "Initial selection DAG" stage I get a DAG with node
t14: ch = store<(store 4 into %ir.p45, align 8, addrspace 1)> t10,
FrameIndex:i32<2>, FrameIndex:i32<3>, undef:i32
1. Where does it come from? Can I do anything to make it not appear?
2. If not, how do I change it so that the operand being stored would be
first loaded into a register, and that register