similar to: [PATCH 08/14] Nested Virtualization: efer

Now that the feature is officially documented (see http://support.amd.com/us/Processor_TechDocs/24593.pdf), I think it makes sense to also allow HVM guests to make use of it. Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Andre Przywara <andre.przywara@amd.com> --- 2010-05-04.orig/xen/arch/x86/hvm/hvm.c 2010-04-22 14:43:25.000000000 +0200 +++ 2010-05-04/xen/arch/x86/hvm/hvm.c

(Applies cleanly only on top of the previously sent SVM/LBR patch.) Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2007-08-08/xen/arch/x86/hvm/svm/svm.c =================================================================== --- 2007-08-08.orig/xen/arch/x86/hvm/svm/svm.c 2007-08-08 11:40:11.000000000 +0200 +++ 2007-08-08/xen/arch/x86/hvm/svm/svm.c 2007-08-08 11:43:53.000000000 +0200

Remove visibility of the FFXSR CPUID bit to an HVM guest. This patch allows HVM Windows x64 to install/boot on AMD-V platforms. This patches applies cleanly to xen-unstable 13743. Please apply to xen-unstable/3.0.5. If possible, pls apply to xen-3.0.4-testing. --Tom thomas.woller@amd.com AMD Corporation 5204 E. Ben White Blvd. UBC1 Austin, Texas 78741 +1-512-602-0059

[PATCH] Clean up x86 control register and MSR macros This patch is based on Rusty's recent cleanup of the EFLAGS-related macros; it extends the same kind of cleanup to control registers and MSRs. It also unifies these between i386 and x86-64; at least with regards to MSRs, the two had definitely gotten out of sync. Signed-off-by: H. Peter Anvin <hpa@zytor.com> diff -urN

[PATCH] Clean up x86 control register and MSR macros This patch is based on Rusty's recent cleanup of the EFLAGS-related macros; it extends the same kind of cleanup to control registers and MSRs. It also unifies these between i386 and x86-64; at least with regards to MSRs, the two had definitely gotten out of sync. Signed-off-by: H. Peter Anvin <hpa@zytor.com> diff -urN

Whether the processor is in 32 or 64-bit mode, if NX is used, then EFER_NX needs to be set. If NX isn''t used, then it''s a "Don''t care". I think bad things happens if you set the NX bit in the page table and don''t have EFER_NX set... -- Mats > -----Original Message----- > From: xen-devel-bounces@lists.xensource.com >

Xen patchbot -unstable <patchbot-unstable@lists.xensource.com> writes: > Fix NX/XD enable on secondary CPUs. > Signed-off-by: Keir Fraser <keir@xensource.com> I think I have this problem with PAE as well. Machine is SMP (hyperthreaded). PAE dom0 boots fine on CPU #0. PAE domU is bound to CPU #1 by default and boots to the login prompt as well, but only with NX disabled (and

From: Yang Zhang <yang.z.zhang@Intel.com> With virtual unrestricted guest feature, L2 guest is allowed to run with PG cleared. Also, allow PAE not set during virtual vmexit emulation. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> --- xen/arch/x86/hvm/hvm.c | 3 ++- xen/arch/x86/hvm/vmx/vvmx.c | 3 +++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.