similar to: [PATCH][SVM] Fix 32bit Windows guest VMs save/restore

Hi, Attached patch implements the VMCB cleanbits SVM feature. Upcoming AMD CPUs introduce them and they are basically hints for the CPU which vmcb values can be re-used from the previous VMRUN instruction. Each bit represents a certain set of fields in the VMCB. Setting a bit tells the cpu it can re-use the cached value from the previous VMRUN. Clearing a bit tells the cpu to reload the values

This patch initializes VMCB CR4 and shadow CR4 with 0 when VMCB is being constructed under nested paging mode. It complies with recent reset_to_realmode change in hvmloader. Signed-off-by: Wei Huang (wei.huang2@amd.com <mailto:wei.huang2@amd.com> ) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85609 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632 _______________________________________________ Xen-devel mailing list

This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP), INTn instruction emulation. Introduce new function vmx_inject_sw_exception() which deliver the software excetion, software interrupt and privileged software exception. Split hardware exception as a seperate function(old function vmx_inject_hw_exception()). Also Passed down intruction length

This patch implements flush by asid feature for AMD CPUs. Thanks, Wei Signed-off-by: Wei Huang <wei.huang2@amd.com> Signed-off-by: Wei Wang <wei.wang2@amd.com> -- Advanced Micro Devices GmbH Sitz: Dornach, Gemeinde Aschheim, Landkreis München Registergericht München, HRB Nr. 43632 WEEE-Reg-Nr: DE 12919551 Geschäftsführer: Alberto Bozzo, Andrew Bowd

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

Direct calls perform better, so we should prefer them and use indirect ones only when there indeed is a need for indirection. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1373,7 +1373,7 @@ void error_interrupt(struct cpu_user_reg void pmu_apic_interrupt(struct cpu_user_regs *regs) { ack_APIC_irq(); -

Hi Ian, There have been a lot of interest on gfx passthru recently. This patch enables ATI VBIOS in passthru mode. The guest VM system BIOS (including Windows boot logo) can now show in passthru screen. We have tested with various Windows and Linux guest VMs. Please help review it. We are also looking forward to comments and suggestions from Xen community users. Signed-off-by: Wei Huang

Attached are the patches to support super page with EPT. We only support 2M size. And shadow may still work fine with 4K pages. The patches can be split into 3 parts. Apply order is as attached. tool.diff To allocate 2M physical contiguous memory in guest except the first 2M and the last 2M. The first 2M covers special memory, and Xen use the last few pages in guest memory to do special

I am adding interrupt support for LWP, whose spec is available at http://support.amd.com/us/Processor_TechDocs/43724.pdf. Basically OS can specify an interrupt vector in LWP_CFG MSR; the interrupt will be triggered when event buffer overflows. For HVM guests, I want to re-inject this interrupt back into the guest VM. Here is one idea similar to virtualized PMU: It first registers a special

flight 5665 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/5665/ Regressions :-( Tests which did not succeed and are blocking: build-amd64-oldkern 4 xen-build fail REGR. vs. 5640 build-amd64 4 xen-build fail REGR. vs. 5640 build-i386-oldkern 4 xen-build fail REGR. vs. 5640

This patch changes hap parameter from boolean to integer. So users can disable and enable hap using "hap=0" and "hap=1". It also prints out nested paging message under SVM. Signed-off-by: Wei Huang <wei.huang2@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

I implemented sysenter for 32-on-64, since it seemed straightforward enough. It mostly works, but every now and again I get vcpus just hanging in blocked state, as if events are being lost or ignored. Its very similar to the symptoms that other people have reported against the pvops kernel, which I have not managed to reproduce. Perhaps using sysenter is exacerbating an existing bug...

This applies to both SVM and VMX. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -310,7 +310,7 @@ static struct keyhandler vmcb_dump_keyha .desc = "dump AMD-V VMCBs" }; -void setup_vmcb_dump(void) +void __init setup_vmcb_dump(void) { register_keyhandler(''v'',

Hi all, Please can anybody explain how communication(direct or indirect) happens between xen and guest os(windows) in full virtualization mode. Both from VMM to guest and from guest to VMM. Thanks and regards, Aditya. __________________________________________________________ Yahoo! India Answers: Share what you know. Learn something new http://in.answers.yahoo.com/

Hi all, I am trying to perform single-stepping and instruction emulation both in Xen-3.2.1. I am using the following approach: First, I mark a guest page "not present" inside the shadow page table so that I could intercept any operation that involves this page. When the guest tries to access that page, it faults and control goes to Xen (sh_page_fault function). There, I emulate that

Future AMD SVM supports a new feature called flush by ASID. The idea is to allow CPU to flush TLBs associated with the ASID assigned to guest VM. So hypervisor doesn''t have to reassign a new ASID in order to flush guest''s VCPU. Please review it. Thanks, Wei Signed-off-by: Wei Huang <wei.huang2@amd.com> Signed-off-by: Wei Wang <wei.wang2@amd.com> -- Advanced Micro

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Xen Security Advisory CVE-2013-1917 / XSA-44 version 2 Xen PV DoS vulnerability with SYSENTER UPDATES IN VERSION 2 ==================== Public release. ISSUE DESCRIPTION ================= The SYSENTER instruction can be used by PV guests to accelerate system call processing. This

In compat mode, the return value here was uninitialized. Signed-off-by: Zachary Amsden <zach@vmware.com> diff -r 1fda49a076ed arch/i386/kernel/sysenter.c --- a/arch/i386/kernel/sysenter.c Fri Apr 06 14:25:09 2007 -0700 +++ b/arch/i386/kernel/sysenter.c Fri Apr 06 14:27:31 2007 -0700 @@ -254,7 +254,7 @@ int arch_setup_additional_pages(struct l { struct mm_struct *mm = current->mm;

In compat mode, the return value here was uninitialized. Signed-off-by: Zachary Amsden <zach@vmware.com> diff -r 1fda49a076ed arch/i386/kernel/sysenter.c --- a/arch/i386/kernel/sysenter.c Fri Apr 06 14:25:09 2007 -0700 +++ b/arch/i386/kernel/sysenter.c Fri Apr 06 14:27:31 2007 -0700 @@ -254,7 +254,7 @@ int arch_setup_additional_pages(struct l { struct mm_struct *mm = current->mm;