similar to: [PATCH 2/2] xsave: extend xsave/xrstor support to all (64) features

XSAVE/XRSTOR manages the existing and future processor extended states on x86 architecture. The XSAVE/XRSTOR infrastructure is defined in Intel SDMs: http://www.intel.com/products/processor/manuals/ The patch uses the classical CR0.TS based algorithm to manage the states on context switch. At present, we know 3 bits in the XFEATURE_ENABLED_MASK: FPU, SSE and YMM. YMM is defined in Intel AVX

Hi, Keir, The following patches refines Xen support for CPU Xsave/Xrestore support. There are four patches included. Patch 1/4: Cleaning up existing Xsave code in Xen. Replace xfeature_low and xfeature_high with a u64 variable xfeature_mask. In structure hvm_vcpu, rename xfeature_mask to xcr0 Provide EDX:EAX with all bits set to 1 for XSAVE and XRSTOR as spec recommends

If a guest sets a state and dirties the state, but later temporarily clears the state, and at this time if this vcpu is scheduled out, then other vcpus may corrupt the state before the vcpu is scheduled in again, thus the state cannot be restored correctly. To solve this issue, this patch save/restore all states unconditionally on vcpu context switch. Signed-off-by: Weidong Han

Attached SVM patch fixes a virtualization of the CPUID NX bit, and cleans up other CPUID bits. Applies cleanly to xen-unstable.hg 10177. Applies to xen-3.0-testing 9696. Please apply to xen-unstable.hg. Please apply to xen-3.0-testing.hg. Tested on top of the KY patches for XCHG (HVM) and SMP SVM support. Keir, Can those 2 patches KY posted last week, also be applied to 3.0.2?

Hi Jan, I was wondering if we should not let the code fall through and clear all registers to zero but rather clear just the one bit we care about? My concern is that a future Intel revision may expand this function and return other information besides that XSAVEOPT, which would then be wiped out by the fall-through code. I''m thinking something like this. Let me know if I have

From: Yang Zhang <yang.z.zhang@Intel.com> We exposed the xsave feature to guest, but we didn''t allow guest to set CR4.OSXSAVE when guest running in nested mode. This will cause win 7 guest fail to use XP mode. In this patch, we allow guest to set CR4.OSXSAVE in nested mode when it has the xsave feature. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> ---

Kashyap: I have not tried integrating your guest xml but I will look over it today when I get a chance. Thank you. Martin: Below is the output from /proc/cpuinfo. Let me know if there is anything else that would be helpful in debugging this. Thank you, Michael Giardino processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 60 model name : Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz stepping

# HG changeset patch # User Paul Durrant <paul.durrant@citrix.com> # Date 1316781326 -3600 # Node ID 55a9ffe0ca81b9b4183626f81fa54343d378704f # Parent cc339ab1d91789ed6ff4d3d9abc1bae2e90ac294 Add save/restore support for viridian APIC assist pfn. c/s 17b754cab7b0 introduced a per-VCPU viridian structure to store the APIC assist pfn. This patch adds support for save and restore of that

Reduce special casing of xen_cpuid() by using cpu capabilities instead of faked cpuid nodes. This cleanup enables us remove the hypervisor specific set_cpu_features callback as the same effect can be reached via setup_[clear|force]_cpu_cap(). Removing the rest faked nodes from xen_cpuid() requires some more work as the remaining cases (mwait leafs and extended topology info) have to be handled

Reduce special casing of xen_cpuid() by using cpu capabilities instead of faked cpuid nodes. This cleanup enables us remove the hypervisor specific set_cpu_features callback as the same effect can be reached via setup_[clear|force]_cpu_cap(). Removing the rest faked nodes from xen_cpuid() requires some more work as the remaining cases (mwait leafs and extended topology info) have to be handled

Here we go, updated patch following your advice checking max leaf and porting cpuidex for subleaf (ECX) 0. NOTE: I’ve set Haswell to be not only 60, but also 63, 69 & 70 model, following changes in Linux kernel & Xen. Also set 62 as Ivy Bridge EP aka E5 v3 (which I has in my workstation). Cheers, -- Adam Detects x86 family 6 model 60, 63, 69, 70 CPU that has AVX2 CPUID leaf 7 subleaf

On Mon, Mar 03, 2014 at 02:15:43PM +0000, Struan Bartlett wrote: > > > On 03/03/2014 13:42, Martin Kletzander wrote: > > On Mon, Mar 03, 2014 at 11:15:51AM +0000, Struan Bartlett wrote: > >> On 03/03/2014 10:55, Martin Kletzander wrote: > >>> On Mon, Mar 03, 2014 at 10:47:03AM +0000, Struan Bartlett wrote: > >>>> On 03/03/2014 10:44, Martin

This patch enables LWP related CPUID to HVM guests. Signed-off-by: Wei Huang <wei.huang2@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

On Tue, Apr 28, 2020 at 05:17:14PM +0200, Joerg Roedel wrote: > From: Mike Stunes <mstunes at vmware.com> > > To avoid a future VMEXIT for a subsequent CPUID function, cache the > results returned by CPUID into an xarray. > > [tl: coding standard changes, register zero extension] > > Signed-off-by: Mike Stunes <mstunes at vmware.com> > Signed-off-by: Tom

On Tue, Apr 28, 2020 at 05:17:14PM +0200, Joerg Roedel wrote: > From: Mike Stunes <mstunes at vmware.com> > > To avoid a future VMEXIT for a subsequent CPUID function, cache the > results returned by CPUID into an xarray. > > [tl: coding standard changes, register zero extension] > > Signed-off-by: Mike Stunes <mstunes at vmware.com> > Signed-off-by: Tom

flight 5665 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/5665/ Regressions :-( Tests which did not succeed and are blocking: build-amd64-oldkern 4 xen-build fail REGR. vs. 5640 build-amd64 4 xen-build fail REGR. vs. 5640 build-i386-oldkern 4 xen-build fail REGR. vs. 5640

On Mon, Mar 03, 2014 at 11:15:51AM +0000, Struan Bartlett wrote: > > On 03/03/2014 10:55, Martin Kletzander wrote: > > On Mon, Mar 03, 2014 at 10:47:03AM +0000, Struan Bartlett wrote: > >> On 03/03/2014 10:44, Martin Kletzander wrote: > >>> On Mon, Mar 03, 2014 at 10:30:11AM +0000, Struan Bartlett wrote: > >>>> Hi Martin > >>>> >

On 5/6/20 1:08 PM, Mike Stunes wrote: > > >> On Apr 28, 2020, at 8:17 AM, Joerg Roedel <joro at 8bytes.org> wrote: >> >> From: Mike Stunes <mstunes at vmware.com> >> >> To avoid a future VMEXIT for a subsequent CPUID function, cache the >> results returned by CPUID into an xarray. >> >> [tl: coding standard changes, register zero

On 03/03/2014 13:42, Martin Kletzander wrote: > On Mon, Mar 03, 2014 at 11:15:51AM +0000, Struan Bartlett wrote: >> On 03/03/2014 10:55, Martin Kletzander wrote: >>> On Mon, Mar 03, 2014 at 10:47:03AM +0000, Struan Bartlett wrote: >>>> On 03/03/2014 10:44, Martin Kletzander wrote: >>>>> On Mon, Mar 03, 2014 at 10:30:11AM +0000, Struan Bartlett wrote:

This is a bug fixing. So it needs go into 4.1. x86: add volatile prefix for cpuid asm clauses cpuid results are possible to be changed now. For example, changing CR4.OSXSAVE bit or setting MSR XCR_XFEATURE_ENABLED_MASK may change XSAVE related cpuid leave return values. The volatile prefix is required to avoid the second cpuid calls following some possible changing operations being optimized in