similar to: How to migrate a linux kernel to xen

Hi, I am soliciting input from the ZFS engineers and/or ZFS users on an extension to "zfs list". Thanks in advance for your feedback. Quick Background: The pNFS project (http://opensolaris.org/os/project/nfsv41/) is adding a new DMU object set type which is used on the pNFS data server to store pNFS stripe DMU objects. A pNFS dataset gets created with the "zfs

Greetings, Does anyone know whether I'll encounter problems serving out CIFS using Samba/CTDB where the servers are pNFS clients? Specifically I'm thinking that I'll have a number of RHEL 6.2 boxes connecting to netapp storage using pNFS. These boxes will then serve a variety of CIFS clients. JR

I just updated a server that's running CentOS 7. I do have elrepo enabled, because this Rave computer has four early Tesla cards. It won't boot. Nor can I get it to boot with either of the other two kernels, and I'll be the one that worked was erased. *Once* it complained that it couldn't fsck the large filesystem (IIRC, it's XFS). The other four-five times, I get pNFS

On Thu, Jun 13, 2013 at 10:52 AM, Guo, Xiaoyi <Xiaoyi.Guo at amd.com> wrote: > I mean something like a target-specific fence machine instruction which > forces ordering of all loads/stores. I want to clarify the meaning of > “noalias” in this case. Is the fence machine instruction considered > “touching” all memory and thus breaks the “noalias” contract? > A fence

On Wed, Jun 12, 2013 at 7:28 PM, Guo, Xiaoyi <Xiaoyi.Guo at amd.com> wrote: > So fence only forces ordering of atomic instructions.**** > > ** ** > > Let me change my question then.**** > > ** ** > > If I have a target-specific intrinsic which forces ordering of ordinary > load/store instructions. Then should it also force ordering of load/stores > to

On Wed, Jun 12, 2013 at 6:17 PM, Guo, Xiaoyi <Xiaoyi.Guo at amd.com> wrote: > Hi, > > I have the following test case: > > define void @foo(<2 x float>* noalias nocapture %out, <2 x float>* > noalias nocapture %data0) nounwind { > entry: > %val1 = load <2 x float>* %data0, align 8 > store <2 x float> %val1, <2 x float>* %out,

I mean something like a target-specific fence machine instruction which forces ordering of all loads/stores. I want to clarify the meaning of "noalias" in this case. Is the fence machine instruction considered "touching" all memory and thus breaks the "noalias" contract? Xiaoyi From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Wednesday, June 12, 2013 8:08

In a multi-threaded environment, in order to ensure the memory ordering expressed by the memory fence, certain memory operations should not be moved across the fence, right? From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Thursday, June 13, 2013 11:18 AM To: Guo, Xiaoyi Cc: LLVM Dev Subject: Re: [LLVMdev] A question w.r.t fence instruction vs. noalias pointer On Thu, Jun 13, 2013 at

On Thu, Jun 13, 2013 at 11:39 AM, Guo, Xiaoyi <Xiaoyi.Guo at amd.com> wrote: > In a multi-threaded environment, in order to ensure the memory ordering > expressed by the memory fence, certain memory operations should not be > moved across the fence, right?**** > > ** > Yes, but operations on noalias pointers don't fall into that category. For noalias pointers, while

Hi, All, Our team within the Software and Services Group at Intel is looking for compiler engineers to join us. Currently two positions are available, see attached links. If you are interested, you can apply online or email me at xiangyang.guo at intel.com. Thanks. --Xiangyang (Mark) Guo

So fence only forces ordering of atomic instructions. Let me change my question then. If I have a target-specific intrinsic which forces ordering of ordinary load/store instructions. Then should it also force ordering of load/stores to noalias pointers in caller functions? Thanks, Xiaoyi From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Wednesday, June 12, 2013 7:06 PM To: Guo,

Hi Andy, Thanks very much for looking into the problem. In this particular test case, it seems most of the time is spent in the sorting, not the grouping. Later, I realized that it seems in this test case most of the expressions to be compared have different length. I tried the following change in compare() when the LHS and RHS's types are the same:

Thank you very much for your reply. Do you mean calculate the hash based on element SCEV pointers? But according to the comments before GroupByComplexity(): /// Note that we go take special precautions to ensure that we get deterministic /// results from this routine. In other words, we don't want the results of /// this to depend on where the addresses of various SCEV objects happened to

On Mon, Jul 29, 2013 at 4:08 PM, Guo, Xiaoyi <Xiaoyi.Guo at amd.com> wrote: > Hi,**** > > ** ** > > We have a benchmark where there are 128 MAD computations in a loop. (See > the attached IR.) Creating SCEVs for these expressions takes a long time, > making the compile time too long. E.g., running opt with the “indvars” pass > only takes 45 seconds.**** > >

Hi Xiaoyi, Do you still see this behavior after r177525? I recently fixed several places where ordering was not propagated, including during legalization. There are probably still cases that are missed, but I'd be interested in seeing a missed case. I'm guessing it's a legalization that expands to multiple new nodes. The AssignOrdering calls in the legalizer may need to be expanded

On Apr 30, 2013, at 11:00 AM, "Guo, Xiaoyi" <Xiaoyi.Guo at amd.com> wrote: > Hi Eric, > > Sorry I wasn’t clear. The problem happened in the “source” pre-RA scheduler, which relies on DAG node ordering to schedule the nodes. In your case, Eric's suggestion was effectively "start implementing fast-isel". Which is not a bad idea if you want to reduce compile

Hi Eric, Sorry I wasn't clear. The problem happened in the "source" pre-RA scheduler, which relies on DAG node ordering to schedule the nodes. Xiaoyi From: Eric Christopher [mailto:echristo at gmail.com] Sent: Tuesday, April 30, 2013 12:54 AM To: Guo, Xiaoyi Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] [PATCH] Propagate DAG node ordering during legalization and

Dear LLVM Team: My name is Guo Xing, a student who are in his third year of college. GSoC2018 is coming, and I want to do some contribution for llvm community. However, the open projects page is for GSoC2017, and some projects like Shell auto-completion support for clang <http://llvm.org/OpenProjects.html#clang-shell-autocompletion-support> have been done. Is there any ideas? What if

On Jul 29, 2013, at 4:08 PM, Guo, Xiaoyi <Xiaoyi.Guo at amd.com> wrote: > Hi, > > We have a benchmark where there are 128 MAD computations in a loop. (See the attached IR.) Creating SCEVs for these expressions takes a long time, making the compile time too long. E.g., running opt with the “indvars” pass only takes 45 seconds. > > It seems that the majority of the time is

Hi Johannes, Silly as me. I just figured out how to correctly use 'alias' metadata. I should define them in IR like below: !3 = !{!3} !4 = !{!4} !5 = !{!5, !3} !6 = !{!6, !4} And then use !5 and !6. The below usage is wrong: !3 = !{!3} !4 = !{!4} Then use !3 and !4 in IR. BR, Terry On Fri, Jul 24, 2020 at 12:12 AM Johannes Doerfert < johannesdoerfert at gmail.com> wrote: