similar to: [Patch 0/4] Refining Xsave/Xrestore support - Version 2

If a guest sets a state and dirties the state, but later temporarily clears the state, and at this time if this vcpu is scheduled out, then other vcpus may corrupt the state before the vcpu is scheduled in again, thus the state cannot be restored correctly. To solve this issue, this patch save/restore all states unconditionally on vcpu context switch. Signed-off-by: Weidong Han

From eee3a3d3072651327453220876ebe9a7345d6ffe Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Tue, 19 Nov 2013 18:44:45 +0800 Subject: [PATCH 2/5] X86 architecture instruction set extension definiation Intel has released new version of Intel Architecture Instruction Set Extensions Programming Reference, add new features like AVX-512, MPX, etc. refer

From a06ea5f6960b7bfa473f5d56762ce3a06b0a2b07 Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Mon, 25 Nov 2013 01:13:12 +0800 Subject: [PATCH 2/4 V2] X86: enable support for new ISA extensions Intel has released new version of Intel Architecture Instruction Set Extensions Programming Reference, adding new features like AVX-512, MPX, etc. Refer to

The first patch really isn''t as much of a follow-up than what triggered the security issues to be noticed in the first place. 1: x86: preserve FPU selectors for 32-bit guest code 2: x86: fix XCR0 handling 3: x86/xsave: adjust state management 4: x86/fxsave: bring in line with recent xsave adjustments The first two I would see as candidates for 4.3 (as well as subsequent backporting,

This patch supports xsave (CPUID:0x0000000D) enumeration for all sub-leaves. In specific, it fixes the following issues: 1. The sub-leaves of CPUID:0x0000000D aren''t contiguous. Hypervisor shouldn''t use register values to stop the enumeration. This patch moves checking on XSAVE sub-leaves out of if-else statement. It also bumps up sub-leaves to 63. 2. It creates a common

XSAVE/XRSTOR manages the existing and future processor extended states on x86 architecture. The XSAVE/XRSTOR infrastructure is defined in Intel SDMs: http://www.intel.com/products/processor/manuals/ The patch uses the classical CR0.TS based algorithm to manage the states on context switch. At present, we know 3 bits in the XFEATURE_ENABLED_MASK: FPU, SSE and YMM. YMM is defined in Intel AVX

Here we go, updated patch following your advice checking max leaf and porting cpuidex for subleaf (ECX) 0. NOTE: I’ve set Haswell to be not only 60, but also 63, 69 & 70 model, following changes in Linux kernel & Xen. Also set 62 as Ivy Bridge EP aka E5 v3 (which I has in my workstation). Cheers, -- Adam Detects x86 family 6 model 60, 63, 69, 70 CPU that has AVX2 CPUID leaf 7 subleaf

I agree with Tim, you need to implement a GetCpuIDAndInfoEx function in Host.cpp and pass the correct value to ecx. Also you need to verify that 7 is a valid leaf because an invalid leaf is defined to return the highest supported leaf on that processor. So if a processor supports say leaf 6 and not leaf 7, then an access leaf 7 will return the data from leaf 6 causing unrelated bits to be

Please CC as I''m not subscribed to valgrind-developers. Under Xen the toolstack is responsible for managing the domains in the system, e.g. creating, destroying, and otherwise manipulating them. To do this it uses a number of ioctls on the /proc/xen/privcmd device. Most of these (the MMAPBATCH ones) simply set things up such that a subsequenct mmap call will map the desired guest

From: Yang Zhang <yang.z.zhang@Intel.com> We exposed the xsave feature to guest, but we didn''t allow guest to set CR4.OSXSAVE when guest running in nested mode. This will cause win 7 guest fail to use XP mode. In this patch, we allow guest to set CR4.OSXSAVE in nested mode when it has the xsave feature. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> ---

On Mon, Sep 8, 2008 at 2:45 PM, Scott Graham <scott.llvm at h4ck3r.net> wrote: > LLVMTypeRef a = LLVMPointerType(LLVMOpaqueType(), 0); > LLVMTypeHandleRef ha = LLVMCreateTypeHandle(a); > LLVMTypeRef atypes[1] = { LLVMResolveTypeHandle(ha) }; > LLVMRefineType(LLVMResolveTypeHandle(ha), LLVMStructType(atypes, 1, 0)); > > Can anyone explain what I'm doing wrong

Hi, I've been using rsync (V 3.09) in non-daemon mode for a while to backup and/or sync various linux machines (sometimes to & from windows shares). I would like to reduce the stuff in my log files to the minimum (as I see it) and cannot find the appropriate parameters to rsync. I can obviously turn all logging off, but would like to see just the names (with path is ok, but not

Hi I'm using the llvm-c wrapper, and trying to build some recursive types (using released 2.3). I get an assert on trying to create a second opaque pointer type after refining a first. The first time through creating an opaque pointer type, a new type is created and returned from PointerType::get, but the second time, ValueType (the opaque type) is found in the PointerTypes map, which seems

Hi, I am currently using the following script to shape traffic on my linux box. I am getting ready to move the script to my linux firewall box so it shapes traffic for my home lan. I am looking to refine my rules a bit so to make bandwidth sharing a bit more efficient. Specifically I am looking to give out bound email more priority so that when a large email is sent, I want it to borrow all

As a follow up to https://reviews.llvm.org/D20217 I would like to use lto/thinlto to refine when a symbol is marked as local/preemptable. I'm not very familiar with lto though so would appreciate some guidance about how best to go about this. Regards Sean Fertile

flight 5665 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/5665/ Regressions :-( Tests which did not succeed and are blocking: build-amd64-oldkern 4 xen-build fail REGR. vs. 5640 build-amd64 4 xen-build fail REGR. vs. 5640 build-i386-oldkern 4 xen-build fail REGR. vs. 5640

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We really don''t want the mmconf window to move/disappear whenever we use is ourselves, not only when we enabled it. Signed-off-by: Jan Beulich <jbeulich@novell.com> --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2297,8 +2297,7 @@ static int emulate_privileged_op(struct goto fail; if ( #ifdef CONFIG_X86_64 - (pci_probe

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