similar to: [patch] Control Machine Check Log output in XEN

Hi, All Following 4 patches are for enabling CMCI of Intel CPUs in XEN. --------------------------------------------------------------------------- Patch 1: remove_intel_mce_old.patch is to remove old p4/p6 files. The reason is that machine check architecture for Intel families including p4/p6/latest are similar. We need not keep duplicated codes. Patch 2: change_stop_machine_run.patch changes

Hi, Jeremy and all This small patch lets pv ops guest handle machine check trap. When non fatal mce error happens, xen will inject vMCE# to the impacted pv ops guest. This patch allows pv ops guest could receive machine check trap and enter its own machine check handler. Thanks & Regards, Criping >From 5efc12fe8214d55e2becc2c4b6ec4a30531d7b60 Mon Sep 17 00:00:00 2001 From: Liping Ke

Hi, all Those days, we spent some efforts to check severe error handling (panic, BUG_ON, BUG, ASSERT) in XEN. We have several round internal discussions as well as several mail threads with Keir. Below is the discussion writeup. If agreed, after review, we want to place it in XEN document folder or XEN wiki since we think it might be helpful to developers. Thanks a lot for your help! Regards,

Hi, all Patch3: Enable CMCI for Intel CPUs -- main patch for CMCI support This patch is the main patch for CMCI enabling in XEN. It removes the old p4/p6 mce files, adds those removed logic to intel common part. Also it adds the new CMCI/MCA intel specific init/interrupt processing, CMCI owner judge algorithm when (bring up CPUs /CPU hotplugs), as well as polling mechanisms, etc. Thanks &

Hi,Keir This patch (Patch 1) is for removing old p4/p6 MCA files. P4/P6 and latest families actually have similar MCA architecture so we cleanup duplicated code. Thanks& Regards, Criping _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Following 7 patches are for PCIE AER (Advanced Error Reporting) support for XEN. --------------------------------------------------------------------------- Patches 1~4 back port from Linux Kernel which enables kernel support to AER. Those patches enable DOM0 PCIE error handling capability. When a device sends a PCIE error message to the root port, it will trigger an interrupt. The irq handler

ioemu-remote: The device model needs to write in the ACPI tables when it wakes up from S3 state. Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com> -- Jean Guyader _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Patch 5 modify_pci: it provides small fix of aerdrv_core, add one new func of get_device by BDF Signed-off-by: Jiang Yunhong<yunhong.jiang@intel.com> Signed-off-by: Ke Liping<liping.ke@intel.com> Thanks& Regards, Criping _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Patch 6 pciback_err_handler.patch: Implementation for enabling PCIE_AER support in XEN This patch is the main implementation for enabling PCIE_AER handling, adding related pci error handler in pciback and pcifront. When a device sends a PCIE error message to the root port, it will triger an interrupt. The irq handler will then collect roor error status register, then schedule a work to process

flight 8270 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/8270/ Regressions :-( Tests which did not succeed and are blocking: test-amd64-amd64-xl-pcipt-intel 5 xen-boot fail REGR. vs. 8256 test-amd64-i386-rhel6hvm-intel 3 host-install(3) broken test-amd64-amd64-win 3 host-install(3) broken test-amd64-i386-pv

[Patch 4/4]: Xend interface for HVM S3 - extend "xm resume <domid>" to be able to S3 resume HVM domain. - when user issue "xm resume" command for HVM domain, xend will use xc lib API to call HVMOP_s3_resume hypercall. Note: it may not appropriate use xm resume for HVM s3, since xm resume is originally designed for save/restor purpose. It will be fine that

Xen/MCE: vMCE injection In our test for win8 guest mce, we find a bug that no matter what SRAO/SRAR error xen inject to win8 guest, it always reboot. The root cause is, current Xen vMCE logic inject vMCE# only to vcpu0, this is not correct for Intel MCE (Under Intel arch, h/w generate MCE# to all CPUs). This patch fix vMCE injection bug, injecting vMCE# to all vcpus. Signed-off-by: Liu,

flight 10504 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/10504/ Regressions :-( Tests which did not succeed and are blocking: test-amd64-amd64-xl-sedf 14 guest-localmigrate/x10 fail REGR. vs. 10491 test-amd64-i386-win 7 windows-install fail REGR. vs. 10491 test-amd64-amd64-xl-winxpsp3 7 windows-install fail REGR. vs. 10491

Jan, This patch just used to stick all 1''s to MCi_CTL, it should not involve much argue, so I sent it separately. Thanks, Jinsong ==================== Xen/MCE: stick all 1''s to MCi_CTL of vMCE This patch is a middle-work patch, prepare for future new vMCE model. It remove mci_ctl array, and keep MCi_CTL all 1''s. Signed-off-by: Liu, Jinsong

flight 10511 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/10511/ Regressions :-( Tests which did not succeed and are blocking: test-amd64-amd64-xl-sedf 14 guest-localmigrate/x10 fail in 10504 REGR. vs. 10491 Tests which are failing intermittently (not blocking): test-amd64-amd64-xl-sedf 13 guest-localmigrate.2 fail pass in 10504 test-i386-i386-win

Sorry, forget to join lists. Regards, Jinsong -----Original Message----- From: Liu, Jinsong Sent: 2007年5月16日 8:23 To: ''Keir Fraser''; Tian, Kevin; xen-devel@lists.xensource.com Subject: RE: [Xen-devel] trap/interrupt gate for hypercall In native linux, syscall (gate type 15) and its RESTORE_ALL code provides weak fixup mechanism when reload segment register, by sending 0

Hi, Keir, Attached are the necessary changes in control panel to support ia64/vti domain builder. One is in common side, and the other is in vti specific image builder. Please take a look, and if no objection, I''d like to ask Dan''s help to check into xen-ia64-unstable.hg first. Signed-off-by Ke Yu <ke.yu@intel.com> Signed-off-by Anthony Xu <anthony.xu@intel.com>

Hi, This introduces send_guest_trap() as preparation for machine check support. send_guest_trap() is designed to inject any trap into a vcpu from NMI/MCE context. This patch makes NMI use of it. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> -- AMD Saxony, Dresden, Germany Operating System Research Center Legal Information: AMD Saxony Limited Liability Company & Co. KG

My hardware is: CPU: Intel(R) Atom(TM) CPU E3845 @ 1.91GHz and it supports EIST(Enhanced Intel SpeedStep Technology). OS: CentOS 7(kernel-3.10) When I set the BIOS options "CPU configuration >> EIST" to "enable", it appears a kernel panic when the system is starting up. Here is what I am seeing: ...... Fast TSC calibration failed. [Hardware Error] CPU 3: Machine Check

This patch adds a check to see if v_end in setup_guest() wraps around to 0 and lets the builder exit gracefully when it does. Signed-off-by: Aravindh Puthiyaparambil <aravindh.puthiyaparambil@unisys.com> > -----Original Message----- > From: Keir Fraser [mailto:Keir.Fraser@cl.cam.ac.uk] > Sent: Thursday, June 01, 2006 6:14 AM > To: Puthiyaparambil, Aravindh > Cc: