similar to: Source code of DomU/Dom0 context switch resulting from writing DomU''s PTE?

Hi: I cannot ping from my guest WinXP to anywhere including Dom0''s IP. Is there any suggest? Here is part of my guest XP''s config info: ============== ... vif = [''type=ioemu, bridge=xenbr0''] ... ============== Thanks! _________________________________________________________________ 新版手机MSN，新功能，新体验！满足您的多彩需求！ http://mobile.msn.com.cn

Backport upstream kernel patch to fix Dom0''s bad pte bug. - In Dom0 kernel, at boot time, system will call bt_ioremap() to do mappings for the Boot Time Fix Memory region. Also system will call bt_iounmap() to unmap the memory region by setting phys=0. In this case, system will encounter pte_ERROR(). This patch backports the upstream kernel patch by Ingo Molnar <mingo@elte.hu>,

Hi: My guest WinXP cannot recognize other USBs except keyboard and mouse. So I cannot send files to my guest except for using network. Is there any suggest? Thanks! _________________________________________________________________ MSN资讯快递，帮助你第一时间了解最新资讯！ http://im.live.cn/newsexpress _______________________________________________ Xen-users mailing list Xen-users@lists.xensource.com

Hi: I intend to use RDTSC to make some time tests in Xen guest WinXP. However, from Intel Developer''s Manual I noticed that RDTSC will cause VMExit if "RETSC exiting" VM-Execution control field is 1. So I wonder: How to query VM-Execution control field in a programmable way? BTW: On Intel Developer''s Manual, it mentioned a method using IA32_VMX_PROCBASED_CTLS MSR,

Add pte_flags() to extract the flags from a pte. This is a special case of pte_val() which is only guaranteed to return the pte's flags correctly; the page number may be corrupted or missing. The intent is to allow paravirt implementations to return pte flags without having to do any translation of the page number (most notably, Xen). Signed-off-by: Jeremy Fitzhardinge

Add pte_flags() to extract the flags from a pte. This is a special case of pte_val() which is only guaranteed to return the pte's flags correctly; the page number may be corrupted or missing. The intent is to allow paravirt implementations to return pte flags without having to do any translation of the page number (most notably, Xen). Signed-off-by: Jeremy Fitzhardinge

Add comment and condense code to make use of native_local_ptep_get_and_clear function. Also, it turns out the 2-level and 3-level paging definitions were identical, so move the common definition into pgtable.h Signed-off-by: Zachary Amsden <zach@vmware.com> diff -r b3bbc1b5e085 include/asm-i386/pgtable-2level.h --- a/include/asm-i386/pgtable-2level.h Wed Apr 11 18:23:44 2007 -0700 +++

Add comment and condense code to make use of native_local_ptep_get_and_clear function. Also, it turns out the 2-level and 3-level paging definitions were identical, so move the common definition into pgtable.h Signed-off-by: Zachary Amsden <zach@vmware.com> diff -r b3bbc1b5e085 include/asm-i386/pgtable-2level.h --- a/include/asm-i386/pgtable-2level.h Wed Apr 11 18:23:44 2007 -0700 +++

Add a pte_update_hook which notifies about pte changes that have been made without using the set_pte / clear_pte interfaces. This allows shadow mode hypervisors which do not trap on page table access to maintain synchronized shadows. It also turns out, there was one pte update in PAE mode that wasn't using any accessor interface at all for setting NX protection. Considering it is PAE

Change pte_clear_full to a more appropriately named pte_clear_not_present, allowing optimizations when not-present mapping changes need not be reflected in the hardware TLB for protected page table modes. There is also another case that can use it in the fremap code. Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> ---

When exiting from an address space, no special hypervisor notification of page table updates needs to occur; direct page table hypervisors, such as Xen, switch to another address space first (init_mm) and unprotects the page tables to avoid the cost of trapping to the hypervisor for each pte_clear. Shadow mode hypervisors, such as VMI and lhype don't need to do the extra work of calling

Now that ptep_establish has a definition in PAE i386 3-level paging code, the only paging model which is insane enough to have multi-word hardware PTEs which are not efficient to set atomically, we can remove the ghost of set_pte_atomic from other architectures which falesly duplicated it, and remove all knowledge of it from the generic pgtable code. set_pte_atomic is now a private pte operator

When exiting from an address space, no special hypervisor notification of page table updates needs to occur; direct page table hypervisors, such as Xen, switch to another address space first (init_mm) and unprotects the page tables to avoid the cost of trapping to the hypervisor for each pte_clear. Shadow mode hypervisors, such as VMI and lhype don't need to do the extra work of calling

Some PTE optimizations for native and paravirt-ops kernels; this provides a huge win for shadow mode hypervisors and gets rid of some unnecessary atomic instructions in native kernels, saving even more on UP by getting rid of implicit LOCK on xchg instruction. Zach

diff -r f1dd818c2f06 include/asm-i386/pgtable-2level.h --- a/include/asm-i386/pgtable-2level.h Thu Oct 19 03:03:09 2006 -0700 +++ b/include/asm-i386/pgtable-2level.h Thu Oct 19 03:03:18 2006 -0700 @@ -22,8 +22,7 @@ #define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) -#define

diff -r f1dd818c2f06 include/asm-i386/pgtable-2level.h --- a/include/asm-i386/pgtable-2level.h Thu Oct 19 03:03:09 2006 -0700 +++ b/include/asm-i386/pgtable-2level.h Thu Oct 19 03:03:18 2006 -0700 @@ -22,8 +22,7 @@ #define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) -#define

Some PTE optimizations for native and paravirt-ops kernels; this provides a huge win for shadow mode hypervisors and gets rid of some unnecessary atomic instructions in native kernels, saving even more on UP by getting rid of implicit LOCK on xchg instruction. Zach

hi, what''s the best way (if at all) to iterate through all of a domain''s page tables within xen 2.0.6? i need to find all references to a specific pte value (which is a given). essentially, a reverse page-table lookup. i''m hesitant to switch to 3.0, but if it''s easier to do what i want, just let me know. thanks, -A. -- Aaron Marks Distributed Systems Lab

In shadow mode hypervisors, ptep_get_and_clear achieves the desired purpose of keeping the shadows in sync by issuing a native_get_and_clear, followed by a call to pte_update, which indicates the PTE has been modified. Direct mode hypervisors (Xen) have no need for this anyway, and will trap the update using writable pagetables. This means no hypervisor makes use of ptep_get_and_clear; there is

In shadow mode hypervisors, ptep_get_and_clear achieves the desired purpose of keeping the shadows in sync by issuing a native_get_and_clear, followed by a call to pte_update, which indicates the PTE has been modified. Direct mode hypervisors (Xen) have no need for this anyway, and will trap the update using writable pagetables. This means no hypervisor makes use of ptep_get_and_clear; there is