similar to: [RFC][PATCH 4/6] HVM PCI Passthrough (non-IOMMU)

The following 5 patches are re-submissions of the vt-d patch. This set of patches has been tested against cs# 15080 and is now much more mature and tested against more environments than the original patch. Specifically, we have successfully tested the patch with following environements: - 32/64-bit Linux HVM guest - 32-bit Windows XP/Vista (64-bit should work but did not test) -

Attached is a patch for shared interrupt between dom0 and HVM domain for vtd. Most of problem is caused by that we should inject interrupt to both domains and the physical interrupt deassertion then may be delayed by the device assigned to the HVM. The patch adds a timer, and the time out value is sufficient large to tolerant the delaying used to wait for the physical interrupt deassertion.

Recently our automated testing system has caught a curious assertion while testing Xen 4.1.5 on a HaswellDT system. (XEN) Assertion ''(sp == 0) || (peoi[sp-1].vector < vector)'' failed at irq.c:1030 (XEN) ----[ Xen-4.1.5 x86_64 debug=n Not tainted ]---- (XEN) CPU: 0 (XEN) RIP: e008:[<ffff82c48016b2b4>] do_IRQ+0x514/0x750 (XEN) RFLAGS: 0000000000010093 CONTEXT:

This patch applies to c/s #15522. Nativedom 1:1 memory enabling - Done by "stealing" memory from Xen''s e820 at boot time. The pages are later being allocated to NativeDom using a special allocator. x86-64 ====== The 512KB-1MB region is remapped (because of the ROMs) to an address above 16MB. As far as NativeDom can see: 1. The 0-512KB

OK, I need to do something like this to io_apic.c - split the hardware specific parts out under mach-default, so we can override them for other subarchitectures. It's not finished, needs header file and makefile work. Would you be willing to take this if I do it? I'm not going to bother if you're not, such refactorings are a pig to maintain out of tree. Frankly, io_apic.c needs a

OK, I need to do something like this to io_apic.c - split the hardware specific parts out under mach-default, so we can override them for other subarchitectures. It's not finished, needs header file and makefile work. Would you be willing to take this if I do it? I'm not going to bother if you're not, such refactorings are a pig to maintain out of tree. Frankly, io_apic.c needs a

@@ -491,16 +512,15 @@ int pirq_guest_bind(struct vcpu *v, int int rc = 0; cpumask_t cpumask = CPU_MASK_NONE; + WARN_ON(!spin_is_locked(&v->domain->evtchn_lock)); I find this WARN_ON() is triggered harmlessly when I assign device to HVM guest. The call trace is XEN_DOMCTL_bind_pt_irq -> pt_irq_create_bind_vtd() -> pirq_guest_bind(). Should we

>>> On 16.05.14 at 10:58, <ijc at hellion.org.uk> wrote: > So it seems like dom0 is unable to (correctly) bind to some hardware > interrupts. I wonder if these messages from Xen's dmesg are relevant. > (XEN) Not enabling x2APIC: depends on iommu_supports_eim. > (XEN) I/O virtualisation disabled > (XEN) Enabled directed EOI with ioapic_ack_old on! The last one

Hi, I saw that Xen support a translation between device/intx to GSI for a single PCI bus, I thought about adding multiple PCI bus support but disregard the bus information so the same device/intx on different buses will be OR wired to the same GSI, sounds reasonable? What other things do I need to support in Xen in order to add multiple PCI buses, assuming that secondary buses holds only

Ever since 3.0.2 we''ve been carrying this patch in our products. Since there was no indication that there would be anything wrong with the ''new'' IO-APIC ack method added back then, we finally decided to drop this patch recently from SLE11, to find that the subsequent release candidate failed to work on at least on system without using "ioapic_ack=old". With

On Tue, Dec 23, 2014 at 06:39:55PM +0800, Vince Hsu wrote: > The flush operation of memory clients is needed for various IP blocks in > the Tegra SoCs to perform a clean reset. > > Signed-off-by: Vince Hsu <vinceh at nvidia.com> > --- > drivers/memory/tegra/mc.c | 21 +++++++++++++++++++++ > include/soc/tegra/mc.h | 23 ++++++++++++++++++++++- > 2 files changed,

Wei, Quick question: Am I reading the code correctly, that even with per-device interrupt remap tables, that GSIs are accounted to the intremap table of the corresponding IOAPIC, presumably because the IOMMU sees interrupts generated as GSIs as coming from the IOAPIC? In that case, then we need all devices sharing the same IOAPIC must not have any vector collisions. Is that correct? -George

We need to write the irq number to GICC_DIR on the physical cpu that previously received the interrupt, but currently we are doing it on the pcpu that received the maintenance interrupt. As a consequence if a vcpu is migrated to a different pcpu, the irq is going to be EOI''ed on the wrong pcpu. This covers the case where dom0 vcpu0 is running on pcpu1 for example (you can test this

The behaviour of default ISRs as provided by the BIOS varies wildly between platforms. Some will simply iret, some will send EOI, some will send EOI and disable the interrupt at the PIC, some will crash the machine due to single-bit errors in the ISR address. When PXENV_UNDI_ISR_IN_START returns PXENV_UNDI_ISR_OUT_NOT_OURS, send the EOI ourselves rather than risking the unpredictable behaviour

Hi, I need a help with tracking down following issue: When trying to boot Xen on a system with Ivy Bridge stepping C0 CPU, it is stuck on CPU initialization. I''ve added some tracing to apic writes/reads and traced it so far to sending INIT IPI. (XEN) HVM: VMX enabled (XEN) HVM: Hardware Assisted Paging detected. (XEN) Setting warm reset code and vector. (XEN) apic_wrmsr (0x280,0x0)

Hi, Keir, These patches are rebased version of Yunhong''s original patches, which were sent out before XEN 3.2 was released. These patches enable MSI support and limited MSI-X support in XEN. Here is the original description of the patches from Yunhong''s mail. The basic idea including: 1) Keep vector global resource owned by xen, while split pirq into per-domain

We need to write the irq number to GICC_DIR on the physical cpu that previously received the interrupt, but currently we are doing it on the pcpu that received the maintenance interrupt. As a consequence if a vcpu is migrated to a different pcpu, the irq is going to be EOI''ed on the wrong pcpu. This covers the case where dom0 vcpu0 is running on pcpu1 for example (you can test this

Hi Stef and Alexey I have read some documents about CBQ algorithm from http://www.icir.org/floyd/cbq.html but still have some question about CBQ in Linux . 1. First estimator can estimate how much bandwidth already USED per class. one estimating algorithm is EWMA (exponential weighted moving average), how about Linux implemenatation about estimator? also do you have link for this algorithm? I

Hyper-V SynIC is a Hyper-V synthetic interrupt controller. The test runs on every vCPU and performs the following steps: * read from all Hyper-V SynIC MSR's * setup Hyper-V SynIC evt/msg pages * setup SINT's routing * inject SINT's into destination vCPU by 'hyperv-synic-test-device' * wait for SINT's isr's completion * clear Hyper-V SynIC evt/msg pages and destroy

Hyper-V SynIC is a Hyper-V synthetic interrupt controller. The test runs on every vCPU and performs the following steps: * read from all Hyper-V SynIC MSR's * setup Hyper-V SynIC evt/msg pages * setup SINT's routing * inject SINT's into destination vCPU by 'hyperv-synic-test-device' * wait for SINT's isr's completion * clear Hyper-V SynIC evt/msg pages and destroy