similar to: How Xen handles Dom1 interrupts?

Hi, I have a question about memory page tables in Xen. As far as I understood, every modification to page table will go through Xen(hypervisor). Is it so that all page tables are actually allocated in Xen(hypervisor) instead of guest OS(domain)? Also, is it the case that Xen(hypervisor) needs to maintain a page table for each process running in every domain? Thanks Haifeng

Hi, I''d like to do some operation every time an hypercall is issued in a domU kernel. I started modifying include/asm-i386/mach-xen/asm/hypercall.h but I don''t think it''s such a great idea, so I think that, as a last chance, I''ll have to substitute all of the hypercall function call with some wrapper function of my own. Can anyone tell me if

Hi, I want my server to be a member of DOM1 but user validation done on DOM2. Can this be done? [global] workgroup = DOM1 netbios name = MYUSERVER security = DOMAIN encrypt passwords = Yes password server = PDC_DOM2,BDC_DOM2 This doesn't work... Any ideas? Thanks, Simon.

Hi, I''m trying to use the SYSCALL/SYSRET opcodes with a minios kernel without much success. Going by the manuals (and linux sources) I first have to setup the STAR and LSTAR registers to define the segment and instruction pointer to be used for SYSCALL: /* * LSTAR and STAR live in a bit strange symbiosis. * They both write to the same internal register. STAR allows

Hello, i''m using the latest Xen 4.0 testing from the mercurial repository and i want to passthrough my Intel Core gpu. But somehow it has a weird IRQ of 1251. So i cant start the vm if i set pci=[''00:02.0'']. The device is bound to the pciback driver correctly. The interesting part of xm dmesg (appears when i start the vm): (XEN) [VT-D]iommu.c:1484: d0:PCI: unmap bdf =

Hello, i''m using the latest Xen 4.0 testing from the mercurial repository and i want to passthrough my Intel Core gpu. But somehow it has a weird IRQ of 1251. So i cant start the vm if i set pci=[''00:02.0'']. The device is bound to the pciback driver correctly. The interesting part of xm dmesg (appears when i start the vm): (XEN) [VT-D]iommu.c:1484: d0:PCI: unmap bdf =

I am having problems installing a custom int3 handler from a com32 app. Here is what I have tried: void int3_handler() { put_str("int3!!!"); __asm__("iret"); } void init_handlers() { struct { unsigned long limit : 16; unsigned long base : 32; } __attribute__((packed)) idtr; __asm__("sidt

Can''t seem to fully boot a domU on either EM64T or Opteron with x86_64 xen-unstable. Both systems'' report this from xen: (XEN) (file=traps.c, line=872) Non-priv domain attempted WRMSR(00000000c0000100. (XEN) (file=traps.c, line=872) Non-priv domain attempted WRMSR(00000000c0000102. (XEN) (file=traps.c, line=880) Non-priv domain attempted RDMSR(00000000c0000080. They boot

On Mon, Aug 24, 2020 at 10:54:37AM +0200, Joerg Roedel wrote: > +#ifdef CONFIG_AMD_MEM_ENCRYPT > +static void set_early_idt_handler(gate_desc *idt, int n, void *handler) > +{ > + struct idt_data data; > + gate_desc desc; > + > + init_idt_data(&data, n, handler); > + idt_init_desc(&desc, &data); > + native_write_idt_entry(idt, n, &desc); > +} >

On Mon, Aug 24, 2020 at 10:54:37AM +0200, Joerg Roedel wrote: > +#ifdef CONFIG_AMD_MEM_ENCRYPT > +static void set_early_idt_handler(gate_desc *idt, int n, void *handler) > +{ > + struct idt_data data; > + gate_desc desc; > + > + init_idt_data(&data, n, handler); > + idt_init_desc(&desc, &data); > + native_write_idt_entry(idt, n, &desc); > +} >

Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.

Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

From: Joerg Roedel <jroedel at suse.de> Hi, here is the fourth version of the SEV-ES Guest Support patches. I addressed the review comments sent to me for the previous version and rebased the code v5.8-rc5. The biggest change in this version is the IST handling code for the #VC handler. I adapted the entry code for the #VC handler to the big pile of entry code changes merged into

From: Joerg Roedel <jroedel at suse.de> Hi, here is the fourth version of the SEV-ES Guest Support patches. I addressed the review comments sent to me for the previous version and rebased the code v5.8-rc5. The biggest change in this version is the IST handling code for the #VC handler. I adapted the entry code for the #VC handler to the big pile of entry code changes merged into

Make a copy of the IDT (as seen via the "sidt" instruction) read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks, and has the added benefit of also not leaking the kernel base offset, if it has been relocated. We already did this on vendor == Intel and family == 5 because of the F0 0F bug -- regardless of if a particular CPU had the F0 0F bug

Make a copy of the IDT (as seen via the "sidt" instruction) read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks, and has the added benefit of also not leaking the kernel base offset, if it has been relocated. We already did this on vendor == Intel and family == 5 because of the F0 0F bug -- regardless of if a particular CPU had the F0 0F bug

From: Joerg Roedel <jroedel at suse.de> Hi, here is the new version of the SEV-ES client enabling patch-set. It is based on the latest tip/master branch and contains the necessary changes. In particular those ar: - Enabling CR4.FSGSBASE early on supported processors so that early #VC exceptions on APs can be handled. - Add another patch (patch 1) to fix a KVM frame-size build

From: Joerg Roedel <jroedel at suse.de> Hi, here is a rebased version of the latest SEV-ES patches. They are now based on latest tip/master instead of upstream Linux and include the necessary changes. Changes to v4 are in particular: - Moved early IDT setup code to idt.c, because the idt_descr and the idt_table are now static - This required to make stack protector work early (or