similar to: [PATCH] Handle p2m_ram_ro with HAP

The lmsw instruction can be used to set CR0_PE, but can never clear it, once set. Currently, as far as I can see, there is no provision to keep lmsw from clearing CR0_PE, either in the vmx code or in x86_emulate code (which is used by SVM to emulate lmsw). This patch fixes this issue. Signed-off-by: Trolle Selander <trolle.selander@eu.citrix.com>

This patch adds a number of fp instructions needed for OS/2 to boot as a HVM guest on Intel/VT hardware. It appears to work fine, and OS/2 is now finally working on Intel/VT as well as AMD/SVM. I''m a little concerned about the "correctness" of the FSTSW emulation and the use of inline assembly directly using the corresponding ops for emulation. Wrt FSTSW, it is really two ops

Also, correct a copy&paste error in the documentation. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- This patch has been in the XenServer patch queue for a long time. It is more for debugging purposes than anything else, but is still proving to be valuable for tracking down bugs with HVM paging operations. diff -r 5af4f2ab06f3 -r e6ec5b2b717f

Hi, I am really confused about NPT walks for guest page table , and eager to know the details about it. It is treated as data writes even if the access itself is a code read in AMD NPT.I just want to know : is it the same in EPT? Could anyone help me? I would like to know that very much Thank you in advance Bo Ma _______________________________________________ Xen-devel mailing list

It was decided during xen patch review that xen map the iomem transparently, so remove xen_set_clr_mmio_pvh_pte() and the sub hypercall PHYSDEVOP_map_iomem. --- arch/x86/xen/mmu.c | 14 -------------- arch/x86/xen/setup.c | 16 ++++------------ include/xen/interface/physdev.h | 10 ---------- 3 files changed, 4 insertions(+), 36 deletions(-) diff --git

"Michael S. Tsirkin" <mst at redhat.com> writes: > On Wed, Jun 05, 2013 at 03:42:57PM -0500, Anthony Liguori wrote: >> "Michael S. Tsirkin" <mst at redhat.com> writes: >> >> Can you explain? I thought the whole trick with separating out the >> virtqueue notification register was to regain the performance? > > Yes but this trick

With KVM, MMIO is much slower than PIO, due to the need to do page walk and emulation. But with EPT, it does not have to be: we know the address from the VMCS so if the address is unique, we can look up the eventfd directly, bypassing emulation. Add an interface for userspace to specify this per-address, we can use this e.g. for virtio. The implementation adds a separate bus internally. This

With KVM, MMIO is much slower than PIO, due to the need to do page walk and emulation. But with EPT, it does not have to be: we know the address from the VMCS so if the address is unique, we can look up the eventfd directly, bypassing emulation. Add an interface for userspace to specify this per-address, we can use this e.g. for virtio. The implementation adds a separate bus internally. This

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

# HG changeset patch # User Olaf Hering <olaf@aepfle.de> # Date 1333120147 -7200 # Node ID 34d9828185501f6e7ea2c3c2a397176a8e54ef0a # Parent 80653c8ea1d19dfe6130396bbc77f766eb9f9fab xenpaging: add error code to indicate iommem passthrough Similar to the existing ENODEV and EXDEV error codes, add EMDEV to indicate that iommu passthrough is not compatible with paging. All error codes are

Hi, We ran a few experiments to compare performance of VMware's paravirtualization technique (VMI) and hardware MMU technologies (HWMMU) on VMware's hypervisor. To give some background, VMI is VMware's paravirtualization specification which tries to optimize CPU and MMU operations of the guest operating system. For more information take a look at this

Hi, We ran a few experiments to compare performance of VMware's paravirtualization technique (VMI) and hardware MMU technologies (HWMMU) on VMware's hypervisor. To give some background, VMI is VMware's paravirtualization specification which tries to optimize CPU and MMU operations of the guest operating system. For more information take a look at this

There has been some progress, but still no joy. Definitely not intended for inclusion at this point. Tim, Wei, I added a Xen command line toggle to disable IOMMU and P2M table sharing. Tim, I verified that changes to p2m-pt.c don''t break shadow mode (64bit hypervisor and Win 7 guest). Hongkaixing, I incorporated your suggestion in patch 2, so I should add your Signed-off-by eventually.

UPDATE: This bug does not reproduce in version: 4.1.4-3 since the domU creation is shadowed by another new bug [1]. Below is my hypervisor log or "xm dmesg" output since the 706543 bug also affects my system: # xm dme (XEN) Xen version 4.1.4 (Debian 4.1.4-3) (waldi at debian.org) (gcc version 4.7.2 (Debian 4.7.2-5) ) Fri Apr 19 11:34:20 UTC 2013 (XEN) Bootloader: GRUB 1.99-27+deb7u1

ioemu-remote: The device model needs to write in the ACPI tables when it wakes up from S3 state. Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com> -- Jean Guyader _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

This fixes a bug in changeset 22526:7a5ee3800417, where the wrong value is read when deciding whether to flush the VTd tables. The effect is minor: in situations where the p2m entry is changed but the mfn is the same, the VTd tables will be unnecessarily flushed. old_entry is left untouched in the second case, since having a present old_entry will cause the an unnecessary check to be taken at

On 15/07/2019 18:28, Andy Lutomirski wrote: > On Mon, Jul 15, 2019 at 9:34 AM Andi Kleen <ak at linux.intel.com> wrote: >> Juergen Gross <jgross at suse.com> writes: >> >>> The long term plan has been to replace Xen PV guests by PVH. The first >>> victim of that plan are now 32-bit PV guests, as those are used only >>> rather seldom these days.

I want to know any difference between writing, reading and shadow page table (for example performance). I am thankful for any help or resource for that. -- Best Regards Mohamad Taghi Mir Mohamad Rezaie Iran University of Science and Technology Department of Computer Science & Engineering System Software Group _______________________________________________ Xen-devel mailing list

I wanted to run without 2MB and 1GB EPT pages, so I added "hap_2mb=0 hap_1gb=0" to the Xen grub command line. However I see the following on Xen boot: (XEN) EPT supports 2MB super page. When I bring up a guest I see a non-zero number of 2MB pages in the "xl create" output: xc: info: VIRTUAL MEMORY ARRANGEMENT: Loader: 0000000000100000->000000000017af10 TOTAL:

This patch initializes VMCB CR4 and shadow CR4 with 0 when VMCB is being constructed under nested paging mode. It complies with recent reset_to_realmode change in hvmloader. Signed-off-by: Wei Huang (wei.huang2@amd.com <mailto:wei.huang2@amd.com> ) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com