Displaying 20 results from an estimated 5000 matches similar to: "[PATCH]: Add support for Intel CPUID Feature mask in Xen"
2013 Jun 25
6
Heterogeneous XCP 1.6 pool
Hi,
I''ve been trying to use E5520 and X5650 together in an heterogeneous pool without success.
I know the combination is not on the official XenServer supported list (http://hcl.xensource.com/CPUPoolsList.aspx), but I thought it would be possible to set the mask anyway and see for myself if the combination works…
My problem is that the mask doesn''t "stick" after a
2014 Aug 26
1
Masking CPU flags via libvirt xml not working?
Hi,
Has anyone here managed to get cpu masking working via libvirt?
Intention to enable VM migrations between hosts of a different CPU
generation.
Inside my xml I'm providing the model as well as a list of features to
specifically disable, but none of it seems to take any effect. On
booting the VM I still see the disabled flags in /proc/cpuinfo
<cpu match='exact'
2010 Mar 02
2
Intel: Overly restrictive test for availablility of CPUID masking MSRs?
Hi,
http://xenbits.xensource.com/xen-unstable.hg?rev/aab9fbd6ffa0 from
http://lists.xensource.com/archives/html/xen-devel/2008-07/msg00518.html
restricts the CPUID masking feature to model 0x1d or model 0x17 with
stepping >=4:
if (!((model == 0x1d) || ((model == 0x17) && ((eax & 0xf) >=
4)))) {
/* fail ... */
A Xeon E5520 which is supposed to
2011 Apr 04
2
ifcpu(64).c32 does not detect Athlon II X4
Hello,
as said in the subject; I am having problems with ifcpu.c32 and
ifcpu64.c32 detecting a Athlon II X4 CPU correctly as a 64Bit capable
CPU. Ifcpu64.c32 does not detect PAE capabilities, also. Both boot the
last (32Bit, non-PAE) entry. On two other Core2-based machines I have
here, everything works.
Can someone tell me what exactly these modules are looking for? Maybe I
can compare that
2010 Sep 17
2
Constant vs Nonstop vs Invariant TSC question
>From /xen-unstable.hg/xen/arch/x86/cpu/intel.c
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
if (cpuid_edx(0x80000007) & (1u<<8)) {
set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
set_bit(X86_FEATURE_NONSTOP_TSC,
2016 Sep 07
0
Hiding hypervisor cpuid bit in Qemu
Hello,
I was hoping someone could help me with an issue I'm having with libvirt 1.3.3 and qemu 2.5.1.
I'm trying to prevent qemu from exposing the 'hypervisor' cupid feature to my VMs. When running qemu directly I can use "-cpu ...,-hypervisor"; which works as expected. Using libvirt, I add "<feature policy='disable' name='hypervisor'/>"
2008 May 13
3
Xen HVM cpuid problem
Hi Keir,
For HVM guests, all cpuid Fn''s going through domain_cpuid()
iterate over the loop and then return 0 for all four registers.
Guests OS''s and cpuid tools in HVM which query for
cpuid Fn 0000.0000 %eax and 8000.0000 %eax, see the value 0 and think,
Xen emulates oldish 386/486 CPUs.
This leads to strange boot failures, "your CPU does not support long mode"
or
2013 Feb 14
3
[PATCH] tools/xend: Only add cpuid and cpuid_check to sexpr once
# HG changeset patch
# User Jim Fehlig <jfehlig@suse.com>
# Date 1360861948 -3600
# Node ID 0f9c7503650fa1b1103b769e1129d66ff614b2ad
# Parent cffb489a6df37d8d114e7d2d53a7a85d14e8f968
tools/xend: Only add cpuid and cpuid_check to sexpr once
When converting a XendConfig object to sexpr, cpuid and cpuid_check
were being emitted twice in the resulting sexpr. The first conversion
writes
2007 Apr 18
3
New CPUID/MSR driver; virtualization hooks
I have finally gotten off the pot and finished writing up my new
CPUID/MSR driver, which contains support for registers that need
arbitrary GPRs touched. For i386 vs x86-64 compatibility, both use an
x86-64 register image (16 64-bit register fields); this allows 32-bit
userspace to access the full 64-bit image if the kernel is 64 bits.
Anyway, this presumably requires new paravirtualization
2007 Apr 18
3
New CPUID/MSR driver; virtualization hooks
I have finally gotten off the pot and finished writing up my new
CPUID/MSR driver, which contains support for registers that need
arbitrary GPRs touched. For i386 vs x86-64 compatibility, both use an
x86-64 register image (16 64-bit register fields); this allows 32-bit
userspace to access the full 64-bit image if the kernel is 64 bits.
Anyway, this presumably requires new paravirtualization
2010 May 11
1
cpuid() fails on Syslinux 4
Hey,
Gert reported me that cpuidtest.c32 reports weird stuff.
After looking at it, I found a potential bug when the cpu vendor isn't
detected from an exisiting list. That will be easy to fix, that's not
the purpose of this mail.
When investigating why the vendor was wrong, I found that a very old
commit in the 4.0 branch generates unexpected results when calling
cpuid().
This commit
2010 Aug 27
3
[PATCH 0/2] [RFC] xl: add cpuid config file option
Hi,
xl is currently ignoring the cpuid= variable in the config file. As I
don''t like the current interface xm exposes (basically because it is
complicated, unintuitive and very error prone), I implemented a new
scheme for specifying CPUID flags policy, combining QEMU''s and Xen''s
approach:
cpuid = "<base>,<feature_name>=[01xks]*,...
The patch includes a
2009 Nov 17
4
''lowest common denominator'' cpuid feature set
I want to be able to test live migration... I have an intel box and an
amd box, so live migration between them won''t ''just work''. From what
I''ve read though, I should be able to use cpuid to turn off all the cpu
features which might be different between them. Is this do-able? I''m
willing to accept any resulting loss of performance etc.
James
2020 May 20
2
[PATCH v3 64/75] x86/sev-es: Cache CPUID results for improved performance
On Tue, Apr 28, 2020 at 05:17:14PM +0200, Joerg Roedel wrote:
> From: Mike Stunes <mstunes at vmware.com>
>
> To avoid a future VMEXIT for a subsequent CPUID function, cache the
> results returned by CPUID into an xarray.
>
> [tl: coding standard changes, register zero extension]
>
> Signed-off-by: Mike Stunes <mstunes at vmware.com>
> Signed-off-by: Tom
2020 May 20
2
[PATCH v3 64/75] x86/sev-es: Cache CPUID results for improved performance
On Tue, Apr 28, 2020 at 05:17:14PM +0200, Joerg Roedel wrote:
> From: Mike Stunes <mstunes at vmware.com>
>
> To avoid a future VMEXIT for a subsequent CPUID function, cache the
> results returned by CPUID into an xarray.
>
> [tl: coding standard changes, register zero extension]
>
> Signed-off-by: Mike Stunes <mstunes at vmware.com>
> Signed-off-by: Tom
2012 Jun 01
5
[PATCH] xl.cfg: document the cpuid= option
# HG changeset patch
# User Olaf Hering <olaf@aepfle.de>
# Date 1338572607 -7200
# Node ID 3da83ff08d6b6431c104a431d6617ccb5977643b
# Parent fde8ad0252ee6ddb8d71dda869db3b20b3d9ca62
xl.cfg: document the cpuid= option
Signed-off-by: Olaf Hering <olaf@aepfle.de>
diff -r fde8ad0252ee -r 3da83ff08d6b docs/man/xl.cfg.pod.5
--- a/docs/man/xl.cfg.pod.5
+++ b/docs/man/xl.cfg.pod.5
@@ -969,9
2016 Dec 03
2
Q: test for CPUID instruction presence
I found that FLAC__cpu_have_cpuid_x86() was removed in the commit
<http://git.xiph.org/?p=flac.git;a=commitdiff;h=fa24613ad94ba8fb8e23bcb9ca80b4548bb617e6>
with the message:
"Remove `FLAC__cpu_have_cpuid_x86` altogether as it wasn't actually
being used but that was difficult to tell because of all the #ifdef
nonsense."
But FLAC__cpu_have_cpuid_x86() actually WAS used
2006 Sep 26
5
powernow-k8: Processor cpuid 681 not supported
I am running 2.6.18-1.2693.fc6xen and I am receiving this message
powernow-k8: Processor cpuid 681 not supported
anyone know if xen works on
processor : 0
vendor_id : AuthenticAMD
cpu family : 6
model : 8
model name : AMD Athlon(tm) Prosussor
stepping : 1
cpu MHz : 1994.985
cache size : 256 KB
fdiv_bug : no
hlt_bug : no
2006 Sep 26
5
powernow-k8: Processor cpuid 681 not supported
I am running 2.6.18-1.2693.fc6xen and I am receiving this message
powernow-k8: Processor cpuid 681 not supported
anyone know if xen works on
processor : 0
vendor_id : AuthenticAMD
cpu family : 6
model : 8
model name : AMD Athlon(tm) Prosussor
stepping : 1
cpu MHz : 1994.985
cache size : 256 KB
fdiv_bug : no
hlt_bug : no
2011 May 30
6
[PATCH] CPUID level 0x00000007:0 (ebx) is word 9, instead of word 7
CPUID level 0x00000007:0 (ebx) is word 9, instead of word 7.
... make it consistent with native Linux.
Signed-off-by: Li Xin <xin.li@intel.com>
diff -r d7c755c25bb9 xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Sat May 28 08:58:08 2011 +0100
+++ b/xen/include/asm-x86/cpufeature.h Tue May 31 07:34:34 2011 +0800
@@ -142,7 +142,7 @@
#define X86_FEATURE_TOPOEXT