similar to: Question related to Single-step execution and Emulation

Hi there, I have a question regarding the functionality of x86_emulate_memop (Xen 3.1) or x86_emulate (Xen 3.2) function. This function gets called from sh_page_fault() function which is invoked when Xen receives a page fault. Since I am not clear completely about the emulation operation performed by Xen, I have following questions with a below mentioned scenario? 1) Suppose I have a memory

Hi all, Does anyone have thoughts on extending v->arch.hvm_vcpu.single_step to support pre-MTF systems, in a way that would mimic the MTF? So far I''m emulating PUSHF/POPF to hide the hypervisor''s trap flag, and eventually I''ll multiplex it down to the guest, but I''m having issues. Right now, I''m enabling X86_EFLAGS_TF in vmx_intr_assist, just like

Hi Bastian, Ian, while I was working on the recent batch of security updates I noticed that the obvious backport of the related patch caused an HVM guest to be crashed as soon as a user inside that guest tried to ptrace a child process. While talking to Jan, I realized that in 4.2 the inject exception code subtly changed in a way that treats TRAP_debug as a HW event (that is triggered by no

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP), INTn instruction emulation. Introduce new function vmx_inject_sw_exception() which deliver the software excetion, software interrupt and privileged software exception. Split hardware exception as a seperate function(old function vmx_inject_hw_exception()). Also Passed down intruction length

Fix the mistake for debug exception(#DB), overflow exception(#OF; generated by INTO) and int 3(#BP) instruction emulation. For INTn (CD ib), it should use type 4 (software interrupt). For INT3 (CC; NOT CD ib with ib=3) and INTO (CE; NOT CD ib with ib=4), it should use type 6 (software exception). For other exceptions (#DE, #DB, #BR, #UD, #NM, #TS, #NP, #SS, #GP, #PF, #MF, #AC, #MC, and #XM), it

Hi, Iam getting the following error ActionController::MethodNotAllowed Only get, put and delete requests are allowed. Actually, Iam trying to have multiple actions for a form to create new record. The actions for the form are cancel, save, publish and preview. here''s the config/routes.rb file code snippet for the relevant controller - Events map.resources :events, :member =>

Hi owen, Can you please elaborate as to what should I do? Find all the instruction which have r2 in it and replace all of them with r1 and then remove the load instruction? Thanks Abhinav ----- Original Message ----- From: "Owen Anderson" <resistor at mac.com> To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> Sent: Friday, November 14, 2008 11:22:32 PM

Hi, I need to install Rmagick to get re-sizing working with Paperclip. My dev machine is on Mac OSX Leopard and the server is on Ubuntu Intrepid 8.1 I dint have Macports or wget at first. I was following this article - http://onrails.org/articles/2007/11/03/installing-rmagick-on-leopard-without-macports-or-fink. Ive done this before too. But some dependency always failed. I want to start with a

r2->replaceAllUsesWith(r1); r2->eraseFromParent(); LLVM makes it easy! ;-) --Owen On Nov 15, 2008, at 11:02 PM, Karhu, Abhinav R wrote: > Hi owen, > Can you please elaborate as to what should I do? Find all the > instruction which have r2 in it and replace all of them with r1 and > then remove the load instruction? > Thanks > Abhinav > ----- Original Message

Here is a second version of my patch from last night. It uses the provided ctype function isspace and does the same readdir(). I remove the rosh_issp() function. I admit to being a bit liberal with my use of braces and spaces. We all of the habit of knowing we can invent a more perfect wheel. Let me know if you have any questions. Keith -------------- next part -------------- A non-text

Hey Guys, Below is a patch for the com32/rosh/rosh.c from tonights syslinx git. The patch does the following: 1) changes the rosh_issp to use an if instead of a case for this simple test. 2) changes the rosh_dir_arg function to move the readdir() to inside the while test. This will let me go through my APUE book. Let me know if you have any questions. Keith --- rosh.orig 2009-03-05

Here are a few warning-removal changes for daemon/: >From eea38a1937ccd396603ed899d829d2982755ea4a Mon Sep 17 00:00:00 2001 From: Jim Meyering <meyering at redhat.com> Date: Thu, 6 Aug 2009 15:25:03 +0200 Subject: [PATCH 1/4] define ATTRIBUTE_UNUSED * daemon/daemon.h (__attribute__, ATTRIBUTE_UNUSED): Define. --- daemon/daemon.h | 10 ++++++++++ 1 files changed, 10 insertions(+), 0

Hi all, Can anybody tell me how to generate a mov instruction in llvm. I found out there is a MemMove Inst but I dont think that is what I want. I want to bypass a load instruction. So i need to generate a mov instruction which will help me remove the redundant load. Thanks -- Abhinav Karhu MS Computer Science Georgia Institute of Technology

BTW. I checked help page of contour and maybe it could mention a note about akima package or interp function. Petr ------- Forwarded message follows ------- From: Petr Pikal <petr.pikal at precheza.cz> To: "Abhinav Verma" <abhinav1205 at gmail.com>, r-help at stat.math.ethz.ch Subject: Re: [R] Reading xyz data from a file and plotting a

pleas help -- Posted via http://www.ruby-forum.com/.

Hi, Attached patch implements the VMCB cleanbits SVM feature. Upcoming AMD CPUs introduce them and they are basically hints for the CPU which vmcb values can be re-used from the previous VMRUN instruction. Each bit represents a certain set of fields in the VMCB. Setting a bit tells the cpu it can re-use the cached value from the previous VMRUN. Clearing a bit tells the cpu to reload the values

On Fri, Nov 14, 2008 at 2:13 PM, Karhu, Abhinav R <akarhu3 at gatech.edu> wrote: > > Hi all, > Can anybody tell me how to generate a mov instruction in llvm. I found out there is a MemMove Inst but I dont think that is what I want. > I want to bypass a load instruction. So i need to generate a mov instruction which will help me remove the redundant load. At the LLVM IL level,

Hi, I want to give direct access to my monitor for my linux domU so that my graphics can run smoothly inside domU which is Ubuntu 8.10 I tried doing the following, but things didn''t work out. 1. I boot my Xen on Debian ( lenny ) using kernel /boot/xen-3.2-1-i386.gz module /boot/vmlinuz-2.6.26-1-xen-686 root=/dev/sdc4 ro console=tty0 pciback.permissive pciback.hide=(00:02.0)

Hey all, I compiled the code using both the -c and -S options. I can get the human readable IR but I still cannot run it using lli. The output of the IR looks like this. Can some of the information tell me about why the program is not running. ; ModuleID = 'Hel.c' target datalayout = "e-p:32:32" target endian = little target pointersize = 32 target triple =