similar to: TSC and Power Management Events on AMD Processors

Lguest currently requires a TSC, which breaks older machines and Matt Mackall who boots the host with "notsc". In addition, there is no good solution to changing TSC speeds (informing all the guests about the TSC impending change before it happens would be a great deal of code and have issues with disobedient guests). This patch makes the host determine if the TSC is both constant and

Lguest currently requires a TSC, which breaks older machines and Matt Mackall who boots the host with "notsc". In addition, there is no good solution to changing TSC speeds (informing all the guests about the TSC impending change before it happens would be a great deal of code and have issues with disobedient guests). This patch makes the host determine if the TSC is both constant and

There is no need to set the same capabilities for each cpu individually. This can be done for all cpus in platform initialization. Cc: Alok Kataria <akataria at vmware.com> Cc: Thomas Gleixner <tglx at linutronix.de> Cc: Ingo Molnar <mingo at redhat.com> Cc: "H. Peter Anvin" <hpa at zytor.com> Cc: x86 at kernel.org Cc: virtualization at lists.linux-foundation.org

Hi, It appears my Xen is stalling right before handing off control to the dom0 kernel. I would appreciate any pointers on where to look next, since I''ve already spent a considerable amount of time trying to figure this one out and nothing turns up. One small detail, with my previous .config, I wasn''t seeing the 4 "(XEN) MCE: MSR 417 is not MCA MSR" at the end of the

Dear list(s), we are running a cluster of virtual machines on ganeti 2.15.2 on top of qemu-kvm 2.1.2. Hosts are Debian jessie (Kernel 3.16). We have big trouble with timekeeping on guests, no matter if these guests are lenny, squeeze, wheezy or jessie. Clock drifts heavily on some, others are fine. There is no obvious pattern on which guest this happens and on which not, but it seems the clock

Dear list(s), we are running a cluster of virtual machines on ganeti 2.15.2 on top of qemu-kvm 2.1.2. Hosts are Debian jessie (Kernel 3.16). We have big trouble with timekeeping on guests, no matter if these guests are lenny, squeeze, wheezy or jessie. Clock drifts heavily on some, others are fine. There is no obvious pattern on which guest this happens and on which not, but it seems the clock

hello, a big time drift appears along time on a guest VM (time is going too slow on the guest). here the setup: ~ physical machine ~ Centos 6.0 x86_64 time set with ntpd Intel(R) Xeon(R) CPU X5650 /proc/cpuinfo shows the "constant_tsc" bit. ~ guest OS ~ Centos 6.0 x86_64 /proc/cpuinfo : processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 13

As a preparation to making Hyper-V TSC page suitable for vDSO move the TSC page reading logic to asm/mshyperv.h. While on it, do the following - Document the reading algorithm. - Simplify the code a bit. - Add explicit READ_ONCE() to not rely on 'volatile'. - Add explicit barriers to prevent re-ordering (we need to read sequence strictly before and after) - Use mul_u64_u64_shr() instead

Implement tsc adjust feature IA32_TSC_ADJUST MSR is maintained separately for each logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the TSC, the logical processor also adds (or subtracts) value X

On Tue, Feb 14, 2017 at 7:50 AM, Vitaly Kuznetsov <vkuznets at redhat.com> wrote: > Thomas Gleixner <tglx at linutronix.de> writes: > >> On Tue, 14 Feb 2017, Vitaly Kuznetsov wrote: >> >>> Hi, >>> >>> while we're still waiting for a definitive ACK from Microsoft that the >>> algorithm is good for SMP case (as we can't

Host S3 implicitly resets the host TSC to 0, but the tsc offset for hvm domains is not recalculated when they resume, causing it to go into negative values. In Linux guest using tsc clocksource, this results in a hang after wrap back to positive values since the tsc clocksource implementation expects it reset. Signed-off-by: Tomasz Wroblewski <tomasz.wroblewski@citrix.com> ---

> On Dec 17, 2015, at 11:58 PM, Earl A Ramirez <earlaramirez at gmail.com> wrote: > I get > the following error: > > [ 0.000000] tsc: Fast TSC calibration failed TSC is a high accuracy CPU clock. TSC can fail due to motherboard hardware fault on multi processor servers. But the kernel usually fails back to the less accurate default hpet clock. Do other versions/kernels work

Hi, I am trying to correlating performance issue in guest VM with the scheduling trace from Xentrace. User-mode application in guest VM periodically dump APIC ID and RDTSC into trace. I also start Xentrace in Dom0 during the same period. However, I notice that range of TSC values report both trace is completely disjointed. TSC values from Xentrace is always greater than what guest VM see, even

>From /xen-unstable.hg/xen/arch/x86/cpu/intel.c if ((c->x86 == 0xf && c->x86_model >= 0x03) || (c->x86 == 0x6 && c->x86_model >= 0x0e)) set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); if (cpuid_edx(0x80000007) & (1u<<8)) { set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); set_bit(X86_FEATURE_NONSTOP_TSC,

Intel recently release a new tsc adjust feature at latest SDM 17.13.3. CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. Basically it is used to simplify TSC synchronization, operation of IA32_TSC_ADJUST MSR is as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the

Minor coding comments > diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h > index d324dce..4ff25436 100644 > --- a/arch/x86/include/asm/mshyperv.h > +++ b/arch/x86/include/asm/mshyperv.h > @@ -178,6 +178,56 @@ void hyperv_cleanup(void); > #endif > #ifdef CONFIG_HYPERV_TSCPAGE > struct ms_hyperv_tsc_page *hv_get_tsc_page(void); > +static

Add proper flushes for TIC and TSC and remove the costly 2D.0110 flush in nv50_flush. Correct TIC and TSC bo sizes. --- src/gallium/drivers/nv50/nv50_context.c | 7 --- src/gallium/drivers/nv50/nv50_context.h | 5 ++ src/gallium/drivers/nv50/nv50_screen.c | 25 ++--------- src/gallium/drivers/nv50/nv50_state_validate.c | 53 +++++++++++++++++++++---

Minor coding comments > diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h > index d324dce..4ff25436 100644 > --- a/arch/x86/include/asm/mshyperv.h > +++ b/arch/x86/include/asm/mshyperv.h > @@ -178,6 +178,56 @@ void hyperv_cleanup(void); > #endif > #ifdef CONFIG_HYPERV_TSCPAGE > struct ms_hyperv_tsc_page *hv_get_tsc_page(void); > +static

Package: xen-hypervisor-3.0.3-1-amd64 Version: 3.0.3-0-2 Severity: important On a machine with 2 dual-core Opterons and 16GB of memory, only about 3GB is detected by the hypervisor. Transcript: root at thismachine:~# xm dmesg Xen version 3.0.3-1 (Debian 3.0.3-0-2) (ultrotter at debian.org) (gcc version 4.1.2 20061028 (prerelease) (Debian 4.1.1-19)) Fri Nov 3 00:21:27 CET 2006 Latest

On Tue, Oct 09, 2018 at 01:09:42PM -0700, Andy Lutomirski wrote: > On Tue, Oct 9, 2018 at 8:28 AM Marcelo Tosatti <mtosatti at redhat.com> wrote: > > > > On Mon, Oct 08, 2018 at 10:38:22AM -0700, Andy Lutomirski wrote: > > > On Mon, Oct 8, 2018 at 8:27 AM Marcelo Tosatti <mtosatti at redhat.com> wrote: > > > > I read the comment three more times and