similar to: Question regarding VM_EXIT and VGA

Hi all, Please can anybody explain how communication(direct or indirect) happens between xen and guest os(windows) in full virtualization mode. Both from VMM to guest and from guest to VMM. Thanks and regards, Aditya. __________________________________________________________ Yahoo! India Answers: Share what you know. Learn something new http://in.answers.yahoo.com/

Oops forgot to change the subject! Please find my email below Sujata Hi, I''m a student working on a research project using xen, and part of what we are doing requires the ability to use the branch tracing facilities of the processor. I.e. we need to be able to write to the IA32_DEBUGCTL MSR and read from the Last Branch Record (LBR) stack (the second of which it appears we can do). We

Hi All, I am trying to provide services to guest VMs where I wish to run guest VMs in a loop. I wish to use a core to schedule a guest VM, service it eg. execute an ISR etc and then return to the context of Xen on that core, so that I can then schedule the next VM on that core. In doing all this, the goal is to avoid the calls to VMEntry and VMExit. Is there a workaround for this to be done or

I recently realized that the original way of dealing with the DebugCtl MSR on VMX failed to make use of the dedicated guest VMCS field. This is being fixed with this patch. What is puzzling me to a certain degree is that while there is a guest VMCS field for this MSR, there''s no equivalent host load field, but there''s also no indication that the MSR would be cleared during a

From: Yang Zhang <yang.z.zhang@Intel.com> The follwoing patches are adding the Posted Interrupt supporting to Xen: Posted Interrupt allows vAPIC interrupts to inject into guest directly without any vmexit. - When delivering a interrupt to guest, if target vcpu is running, update Posted-interrupt requests bitmap and send a notification event to the vcpu. Then the vcpu will handle this

This patch series enables the Last Branch Recording feature for the guest. Instead of trapping each LBR stack MSR access, the MSRs are passthroughed to the guest. Those MSRs are switched (i.e. load and saved) on VMExit and VMEntry. Test: Try "perf record -b ./test_program" on guest. Wei Wang (4): KVM/vmx: re-write the msr auto switch feature KVM/vmx: auto switch

This patch series enables the Last Branch Recording feature for the guest. Instead of trapping each LBR stack MSR access, the MSRs are passthroughed to the guest. Those MSRs are switched (i.e. load and saved) on VMExit and VMEntry. Test: Try "perf record -b ./test_program" on guest. Wei Wang (4): KVM/vmx: re-write the msr auto switch feature KVM/vmx: auto switch

> + > +/* The exitcode is in native SVM/VMX format. The forced exitcode > + * is in generic format. > + */ Introducing a 3rd format of exitcode is over-complicated IMO. > +enum nestedhvm_vmexits > +nestedhvm_vcpu_vmexit(struct vcpu *v, struct cpu_user_regs *regs, > + uint64_t exitcode) > +{ I doubt about the necessary of this kind of wrapper. In single layer

Keir, is there a particular reason you chose to use slightly different special mode numbers than Linux, ignoring VIDEO_CURRENT_MODE altogether? I think it wouldn''t be bad to be in sync with Linux here, and I independently think that having a way to avoid mode switching altogether is good to have in case of possible problems on exotic hardware. Jan

Changes from v2 to v3: - Use pfn_to_paddr() to get the address from frame number instead of doing shift directly. - Remove some unnecessary initialization code and add "static" to vmentry_fields and gpdptr_fields. - Enable the VMREAD/VMWRITE bitmap only if nested hvm is enabled. - Use clear_page() to set all 0 to the page instead of memset(). - Use domheap to allocate the

Hi, I''m a student working on a research project using xen, and part of what we are doing requires the ability to use the branch tracing facilities of the processor. I.e. we need to be able to write to the IA32_DEBUGCTL MSR and read from the Last Branch Record (LBR) stack (the second of which it appears we can do). We saw a thread discussing this:

Various versions of Linux under various circumstances select TSC as the primary clocksource for the kernel. This is especially true for uniprocessor kernels, but also in some cases for multiprocessor kernels. In most cases, this is because a processor bit (tsc_invariant? constant_tsc?) is passed through directly from the hardware via Xen and tested by the hvm guest and the result implies that

From: Yang Zhang <yang.z.zhang@Intel.com> The following patches fix the issue that fail to boot L2 guest on APIC-v available machine. The main problem is that with APIC-v, virtual interrupt inject L1 is totally through APIC-v. But if virtual interrupt is arrived when L2 is running, L1 will detect interrupt through vmexit with reason external interrupt. If this happens, we should update

On Wed, Jun 03, 2020 at 04:23:25PM +0200, Joerg Roedel wrote: > > > + */ > > > + io_bytes = (exit_info_1 >> 4) & 0x7; > > > + ghcb_count = sizeof(ghcb->shared_buffer) / io_bytes; > > > + > > > + op_count = (exit_info_1 & IOIO_REP) ? regs->cx : 1; > > > + exit_info_2 = min(op_count, ghcb_count); > > > +

On Wed, Jun 03, 2020 at 04:23:25PM +0200, Joerg Roedel wrote: > > > + */ > > > + io_bytes = (exit_info_1 >> 4) & 0x7; > > > + ghcb_count = sizeof(ghcb->shared_buffer) / io_bytes; > > > + > > > + op_count = (exit_info_1 & IOIO_REP) ? regs->cx : 1; > > > + exit_info_2 = min(op_count, ghcb_count); > > > +

I''m not seeing the problem that Fan Zhao is reporting, instead I get this one. Not sure if ti''s the same one or a different problem... This happens with my simple-guest [i.e. not using hvmloader, as I described before]. This worked fine yesterday. (XEN) event_channel.c:178:d0 EVTCHNOP failure: domain 0, error -22, line 178 (XEN) bad shared page: 0 (XEN) domain_crash_sync called

ioemu-remote: The device model needs to write in the ACPI tables when it wakes up from S3 state. Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com> -- Jean Guyader _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Removing silly virtio-dev@ list because it's bouncing mail... On 12/07/2016 08:21 AM, David Hildenbrand wrote: >> Li's current patches do that. Well, maybe not pfn/length, but they do >> take a pfn and page-order, which fits perfectly with the kernel's >> concept of high-order pages. > > So we can send length in powers of two. Still, I don't see any

Removing silly virtio-dev@ list because it's bouncing mail... On 12/07/2016 08:21 AM, David Hildenbrand wrote: >> Li's current patches do that. Well, maybe not pfn/length, but they do >> take a pfn and page-order, which fits perfectly with the kernel's >> concept of high-order pages. > > So we can send length in powers of two. Still, I don't see any

On Tue, Apr 28, 2020 at 05:16:35PM +0200, Joerg Roedel wrote: > From: Tom Lendacky <thomas.lendacky at amd.com> > > Add support for decoding and handling #VC exceptions for IOIO events. > > Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com> > [ jroedel at suse.de: Adapted code to #VC handling framework ] > Co-developed-by: Joerg Roedel <jroedel at