similar to: Migration filesystem coherency?

Hello, I''m currently trying to understand some problems I had in the past with mixing look-back with blktap(2) for HV and PV domains. I''m stuck reading the source code, so I''d like to get some help from the list. Interrupt me if I got something fundamentally wrong in my understanding so far: 1. With pure-HV the domU gets an emulated IDE (or whatever) disk. The

Hello, Has any more work been done on this front? The message below is from Sept. 2006. In particular, the LT/TXT Technology Enabling Platform (TEP) is now available from MPC Corp. Where can one obtain an appropriate AC SINIT module (i.e., like lpg_sinit_20050831_pae.auth.bin below)? I would like to begin using Xen with TXT support. Thanks, -Jon This patch adds SMP support to the

We''ve been noticing a lot of these errors when booting VMs since we moved to 3.0.3 - I''ve traced this to the hotplug scripts in Dom0 taking >10s to run to completion and specifically the vif-bridge script taking >=9s to plug the vif into the s/w bridge on occasion - was wondering if anyone has any insight into why it might take this long. I added some instrumentation to

Hi All, I have two time series, each has length 354. I tried to calculate the coherency^2 between them, but the value I got is always 1. On a website, it says: " Note that if the ensemble averaging were to be omitted, the coherency (squared) would be 1, independent of the data". Does any of you know how to specify properly in R in order to get more useful coherency? The examples in

This patch adds SMP support to the previous version. Since that has not been merged I have included it in this patch. This should apply cleanly to the tip. Below is the text of the original submittal, slightly updated. Attached is a preliminary patch that adds Intel(R) LaGrande Technology (LT) (Safer Mode Extensions - SMX) support to Xen. While there are still several enhancements needed for

Currently, default behavior of O_DIRECT writes was allowing concurrent writing among nodes, no cluster coherency guaranteed (no EX locks was taken), it hurts buffered reads on other nodes by reading stale data from cache. The new mount option introduce a chance to choose two different behaviors for O_DIRECT writes: * coherency=full, as the default value, will disallow concurrent

On Thu, Feb 02, 2017 at 04:40:49PM +0000, Will Deacon wrote: > On Thu, Feb 02, 2017 at 06:30:28PM +0200, Michael S. Tsirkin wrote: > > I am inclined to say, for 4.10 let's revert > > c7070619f3408d9a0dffbed9149e6f00479cf43b since what it fixes is not a > > regression in 4.10. > > No complaints there, as long as we can keep working to fix this for 4.11 > and

On Thu, Feb 02, 2017 at 04:40:49PM +0000, Will Deacon wrote: > On Thu, Feb 02, 2017 at 06:30:28PM +0200, Michael S. Tsirkin wrote: > > I am inclined to say, for 4.10 let's revert > > c7070619f3408d9a0dffbed9149e6f00479cf43b since what it fixes is not a > > regression in 4.10. > > No complaints there, as long as we can keep working to fix this for 4.11 > and

On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote: > On Thu, Feb 09, 2017 at 08:17:16PM +0200, Michael S. Tsirkin wrote: > > On Thu, Feb 02, 2017 at 04:40:49PM +0000, Will Deacon wrote: > > > On Thu, Feb 02, 2017 at 06:30:28PM +0200, Michael S. Tsirkin wrote: > > > > I am inclined to say, for 4.10 let's revert > > > >

On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote: > On Thu, Feb 09, 2017 at 08:17:16PM +0200, Michael S. Tsirkin wrote: > > On Thu, Feb 02, 2017 at 04:40:49PM +0000, Will Deacon wrote: > > > On Thu, Feb 02, 2017 at 06:30:28PM +0200, Michael S. Tsirkin wrote: > > > > I am inclined to say, for 4.10 let's revert > > > >

On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote: > On ARM (and other archs such as > Power), having a mismatch between a cacheable and a non-cacheable mapping > can result in a loss of coherency between the two (for example, if the > non-cacheable gues accesses bypass the cache, but the cacheable host > accesses allocate in the cache). I guess it's an optimization

On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote: > On ARM (and other archs such as > Power), having a mismatch between a cacheable and a non-cacheable mapping > can result in a loss of coherency between the two (for example, if the > non-cacheable gues accesses bypass the cache, but the cacheable host > accesses allocate in the cache). I guess it's an optimization

By forcing on DMA API usage for ARM systems, we have inadvertently kicked open a hornets' nest in terms of cache-coherency. Namely that unless the virtio device is explicitly described as capable of coherent DMA by firmware, the DMA APIs on ARM and other DT-based platforms will assume it is non-coherent. This turns out to cause a big problem for the likes of QEMU and kvmtool, which generate

By forcing on DMA API usage for ARM systems, we have inadvertently kicked open a hornets' nest in terms of cache-coherency. Namely that unless the virtio device is explicitly described as capable of coherent DMA by firmware, the DMA APIs on ARM and other DT-based platforms will assume it is non-coherent. This turns out to cause a big problem for the likes of QEMU and kvmtool, which generate

I am having a hard time interpreting the phase and coherency plots. x is two timeseries that occur at the same time i.e. a b 1 11.2 12.3 16 11.3 12.4 31 11.4 12.5 46 11.5 12.6 ...etc even though my example is does not show this they are oscillating at more or less the same frequency just shifted by t=x (imagine two sine waves offset with the 2nd sine

RHEL5 32bit xen 3.3.0 rpms? Anyone? ;) _______________________________________________ Xen-users mailing list Xen-users@lists.xensource.com http://lists.xensource.com/xen-users

We have found a critical problem with the XEN 3.1 release (for those who are running 15-20 VMs on a single server). We are using the official XEN 3.1 release on a rackable server (Dual-Core AMD Opteron, 8GB RAM). The problem we are seeing is that intermittently vifs fail to work properly in VMs after we create around 15-17 VMs on our server (all running at the same time, created one by

On 02/01/2017 08:19 PM, Michael S. Tsirkin wrote: > On Wed, Feb 01, 2017 at 06:27:09PM +0000, Will Deacon wrote: >> On Wed, Feb 01, 2017 at 08:09:21PM +0200, Michael S. Tsirkin wrote: >>> On Wed, Feb 01, 2017 at 12:25:57PM +0000, Robin Murphy wrote: >>>> diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c >>>> index

On 02/01/2017 08:19 PM, Michael S. Tsirkin wrote: > On Wed, Feb 01, 2017 at 06:27:09PM +0000, Will Deacon wrote: >> On Wed, Feb 01, 2017 at 08:09:21PM +0200, Michael S. Tsirkin wrote: >>> On Wed, Feb 01, 2017 at 12:25:57PM +0000, Robin Murphy wrote: >>>> diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c >>>> index

Hi All, I am working on creating storage driver domain with xen-4.3.0 . I am referring this - http://wiki.xen.org/wiki?title=Storage_driver_domains&oldid=9371 I have created Storage domain with xl utility of xen, then followed above wiki for rest of the steps, additionally I did install blktap-dkms package also- Following xen processes are running on Domain 0: