similar to: [PATCH] Mask off the reserved features in cpuid (ecx = 1)

Hi, Please find below the proposal for the generic use of cpuid space allotted for hypervisors. Apart from this cpuid space another thing worth noting would be that, Intel & AMD reserve the MSRs from 0x40000000 - 0x400000FF for software use. Though the proposal doesn't talk about MSR's right now, we should be aware of these reservations as we may want to extend the way we use CPUID to

Hi, Please find below the proposal for the generic use of cpuid space allotted for hypervisors. Apart from this cpuid space another thing worth noting would be that, Intel & AMD reserve the MSRs from 0x40000000 - 0x400000FF for software use. Though the proposal doesn't talk about MSR's right now, we should be aware of these reservations as we may want to extend the way we use CPUID to

Hi, all Some Latest Intel CPU models (CPUID.1.EAX >= 0x00010674) support cupid mask features. Cpuid feature mask is used to limit the feature flags reported by CPUID.1.EDX:ECX. This small patch adds CPUID feature mask support in XEN by adding boot options in Grub entry as below example: kernel /boot/xen.gz com1=115200,8n1 console=com1 cpuid_mask_ecx = 0xFFFF7FFF cpuid_mask_edx = 0xFFFFFFFC

On Thu, Sep 18, 2014 at 10:42 AM, Nakajima, Jun <jun.nakajima at intel.com> wrote: > On Thu, Sep 18, 2014 at 10:20 AM, KY Srinivasan <kys at microsoft.com> wrote: >> >> >>> -----Original Message----- >>> From: Paolo Bonzini [mailto:paolo.bonzini at gmail.com] On Behalf Of Paolo >>> Bonzini >>> Sent: Thursday, September 18, 2014 10:18

On Thu, Sep 18, 2014 at 10:42 AM, Nakajima, Jun <jun.nakajima at intel.com> wrote: > On Thu, Sep 18, 2014 at 10:20 AM, KY Srinivasan <kys at microsoft.com> wrote: >> >> >>> -----Original Message----- >>> From: Paolo Bonzini [mailto:paolo.bonzini at gmail.com] On Behalf Of Paolo >>> Bonzini >>> Sent: Thursday, September 18, 2014 10:18

Quite frankly it might make more sense to define a cross-VM *cpuid* range. The cpuid leaf can just point to the MSR. The big question is who will be willing to be the registrar. On September 18, 2014 11:35:39 AM PDT, Andy Lutomirski <luto at amacapital.net> wrote: >On Thu, Sep 18, 2014 at 10:42 AM, Nakajima, Jun ><jun.nakajima at intel.com> wrote: >> On Thu, Sep 18, 2014

On Thu, Sep 18, 2014 at 6:28 PM, Andy Lutomirski <luto at amacapital.net> wrote: > On Thu, Sep 18, 2014 at 6:03 PM, Andy Lutomirski <luto at amacapital.net> wrote: >> On Thu, Sep 18, 2014 at 5:49 PM, Nakajima, Jun <jun.nakajima at intel.com> wrote: >>> On Thu, Sep 18, 2014 at 3:07 PM, Andy Lutomirski <luto at amacapital.net> wrote: >>>

On Thu, Sep 18, 2014 at 6:28 PM, Andy Lutomirski <luto at amacapital.net> wrote: > On Thu, Sep 18, 2014 at 6:03 PM, Andy Lutomirski <luto at amacapital.net> wrote: >> On Thu, Sep 18, 2014 at 5:49 PM, Nakajima, Jun <jun.nakajima at intel.com> wrote: >>> On Thu, Sep 18, 2014 at 3:07 PM, Andy Lutomirski <luto at amacapital.net> wrote: >>>

On Thu, Sep 18, 2014 at 5:49 PM, Nakajima, Jun <jun.nakajima at intel.com> wrote: > On Thu, Sep 18, 2014 at 3:07 PM, Andy Lutomirski <luto at amacapital.net> wrote: > >> So, as a concrete straw-man: >> >> CPUID leaf 0x48000000 would return a maximum leaf number in EAX (e.g. >> 0x48000001) along with a signature value (e.g. "CrossHVPara\0") in

On Thu, Sep 18, 2014 at 5:49 PM, Nakajima, Jun <jun.nakajima at intel.com> wrote: > On Thu, Sep 18, 2014 at 3:07 PM, Andy Lutomirski <luto at amacapital.net> wrote: > >> So, as a concrete straw-man: >> >> CPUID leaf 0x48000000 would return a maximum leaf number in EAX (e.g. >> 0x48000001) along with a signature value (e.g. "CrossHVPara\0") in

> -----Original Message----- > From: Paolo Bonzini [mailto:paolo.bonzini at gmail.com] On Behalf Of Paolo > Bonzini > Sent: Thursday, September 18, 2014 10:18 AM > To: Nakajima, Jun; KY Srinivasan > Cc: Mathew John; Theodore Ts'o; John Starks; kvm list; Gleb Natapov; Niels > Ferguson; Andy Lutomirski; David Hepkin; H. Peter Anvin; Jake Oshins; Linux > Virtualization

> -----Original Message----- > From: Paolo Bonzini [mailto:paolo.bonzini at gmail.com] On Behalf Of Paolo > Bonzini > Sent: Thursday, September 18, 2014 10:18 AM > To: Nakajima, Jun; KY Srinivasan > Cc: Mathew John; Theodore Ts'o; John Starks; kvm list; Gleb Natapov; Niels > Ferguson; Andy Lutomirski; David Hepkin; H. Peter Anvin; Jake Oshins; Linux > Virtualization

On Sep 19, 2014 9:40 AM, "H. Peter Anvin" <hpa at zytor.com> wrote: > > On 09/19/2014 09:14 AM, Nakajima, Jun wrote: > > > > I slept on it, and I think using the CPUID instruction alone would be > > simple and efficient: > > - We have a huge space for CPUID leaves > > - CPUID also works for user-level > > - It can take an additional 32-bit

On Sep 19, 2014 9:40 AM, "H. Peter Anvin" <hpa at zytor.com> wrote: > > On 09/19/2014 09:14 AM, Nakajima, Jun wrote: > > > > I slept on it, and I think using the CPUID instruction alone would be > > simple and efficient: > > - We have a huge space for CPUID leaves > > - CPUID also works for user-level > > - It can take an additional 32-bit

On Thu, Sep 18, 2014 at 10:20 AM, KY Srinivasan <kys at microsoft.com> wrote: > > >> -----Original Message----- >> From: Paolo Bonzini [mailto:paolo.bonzini at gmail.com] On Behalf Of Paolo >> Bonzini >> Sent: Thursday, September 18, 2014 10:18 AM >> To: Nakajima, Jun; KY Srinivasan >> Cc: Mathew John; Theodore Ts'o; John Starks; kvm list; Gleb

On Thu, Sep 18, 2014 at 6:03 PM, Andy Lutomirski <luto at amacapital.net> wrote: > On Thu, Sep 18, 2014 at 5:49 PM, Nakajima, Jun <jun.nakajima at intel.com> wrote: >> On Thu, Sep 18, 2014 at 3:07 PM, Andy Lutomirski <luto at amacapital.net> wrote: >> >>> So, as a concrete straw-man: >>> >>> CPUID leaf 0x48000000 would return a maximum

Defining a standard way of transferring random numbers between the host and the guest is an excellent idea. As the person who writes the RNG code in Windows, I have a few comments: DETECTION: It should be possible to detect this feature through CPUID or similar mechanism. That allows the code that uses this feature to be written without needing the ability to catch CPU exceptions. I could be

Defining a standard way of transferring random numbers between the host and the guest is an excellent idea. As the person who writes the RNG code in Windows, I have a few comments: DETECTION: It should be possible to detect this feature through CPUID or similar mechanism. That allows the code that uses this feature to be written without needing the ability to catch CPU exceptions. I could be

Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

See http://lkml.org/lkml/2008/10/1/246 for more context. Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2008-10-27/xen/arch/x86/domain.c =================================================================== --- 2008-10-27.orig/xen/arch/x86/domain.c 2008-11-11 16:24:48.000000000 +0100 +++ 2008-10-27/xen/arch/x86/domain.c 2008-11-19 10:22:34.000000000 +0100 @@ -1888,6 +1888,8 @@ void