Displaying 20 results from an estimated 4000 matches similar to: "Triple relationship"
2006 Jul 20
2
search on fields
Hi,
I wonder if it is possible to perform the "find_by_contents" on a subset
of fields indexed in acts_as_ferret.If so, how?
In my code I have:
acts_as_ferret (:fields => [''title'', ''focus'', ''purpose''])
However, I like to have two search options one on all fields and one
only on the title.
Any help is most appreciated.
2016 Jan 20
4
Executing OpenMP 4.0 code on Nvidia's GPU
Hi Arpith,
That is exactly what it is :).
My bad, I thought I copied over the libraries to where LIBRARY_PATH
pointing but apparently it was copied to a wrong destination.
Thanks a lot.
On Wed, Jan 20, 2016 at 4:51 AM, Arpith C Jacob <acjacob at us.ibm.com> wrote:
> Hi Ahmed,
>
> nvlink is unable to find the GPU OMP runtime library in its path. Does
> LIBRARY_PATH point to
2015 Apr 08
5
[LLVMdev] CUDA front-end (CUDA to LLVM IR)
Hi,
I wanted to ask whether there is ongoing effort (or an already established
tool) that enables to convert CUDA kernels (that uses CUDA specific
intrinsics, e.g., threadId.x, __syncthreads(), ...) to LLVM IR. I am aware
that I can do this for OpenCL with the help of libclc but I can not find
something similar for CUDA.
Thanks
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2006 Jun 26
4
Migrations and svn branches...
We are currently doing some development on a variety of branches that
each have their own set of migrations (gee, database changes on a
branch? how novel). The problem is with this strictly linear numbering
of the migrations and these alternate branches.
Let''s suppose I have branches/foo that adds two migrations
024_add_foo.rb and 025_refine_foo.rb
and then another branches/bar
2015 Apr 08
2
[LLVMdev] CUDA front-end (CUDA to LLVM IR)
On Wed, Apr 8, 2015 at 10:12 AM, Dmitry Mikushin <dmitry at kernelgen.org>
wrote:
> A tool of this kind here: https://github.com/apc-llc/nvcc-llvm-ir
>
> 2015-04-08 19:01 GMT+02:00 Ahmed ElTantawy <ahmede at ece.ubc.ca>:
>
>> Hi,
>>
>> I wanted to ask whether there is ongoing effort (or an already
>> established tool) that enables to convert CUDA
2008 Aug 12
1
No answer in anova.nls
Dear R-helpers,
I am trying to check whether a model of the form y(t) = a/(1 +b*t) fits the
curve of downloads per day of a file in a specific online community better
than a model of the form y(t) = a*exp(-b*t). For that, I used nls to fit
both models and I am now trying to compare the fits with anova. The problem
I find is that anova does not report an F statistic or a p-value when I
compare
2012 Jun 13
0
[LLVMdev] non-SSA IR generation
Hi Amruth,
If you do not specify any optimization flag for 'clang' and do not run 'opt
-mem2reg' pass on the generated IR file, it is in non-SSA form. However,
many variables stay in memory instead of registers in this case.
Thanks,
Jiesheng
On Wed, Jun 13, 2012 at 1:17 PM, <amruth.rd at knights.ucf.edu> wrote:
> I am experimenting with LLVM optimizer and found that
2018 Jan 30
3
Disable spilling sub-registers in LLVM
Right Matthias, I am aware that an implementation for
storeRegToStackSlot()/loadRegFromStackSlot() is necessary. But these
functions receive the physical register that need to be spilled, they
might receive the sub-register. In this case, using the super-register
naively is unsafe (e.g., one might overwrite parts of it). Thus, I think
the register allocator/spillar need to be aware of the
2012 Jun 13
3
[LLVMdev] non-SSA IR generation
I am experimenting with LLVM optimizer and found that the bit code file clang emits is already in SSA form, but I want to generate it in non-SSA form. Would you let me know if there is any way of doing it?
Cheera,Amruth
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2018 Jan 30
0
Disable spilling sub-registers in LLVM
To make my point clear, I believe an implementation of
storeRegToStackSlot()/loadRegFromStackSlot() is not sufficient (as it
received the physical register already). Does this make sense?
On 2018-01-30 13:33, ahmede wrote:
> Right Matthias, I am aware that an implementation for
> storeRegToStackSlot()/loadRegFromStackSlot() is necessary. But these
> functions receive the physical
2012 Jun 14
1
[LLVMdev] non-SSA IR generation
Well, it *is* in SSA form, but it "cheats" by keeping values in memory.
--Sean Silva
On Wed, Jun 13, 2012 at 2:00 PM, Jiesheng Wei <jwei at ece.ubc.ca> wrote:
> Hi Amruth,
>
> If you do not specify any optimization flag for 'clang' and do not run
> 'opt -mem2reg' pass on the generated IR file, it is in non-SSA form.
> However, many variables stay
2018 Jan 30
3
Disable spilling sub-registers in LLVM
Hi Quentin,
Let me clarify if I understood this correctly.
If the accesses (writes and reads) to sub-registers are expressed always
as sub-registers of the super-register register class (e.g.,
SuperReg.sub1;), then the spilling decision is for the super register.
But, if the accesses are in terms of the register class of the
sub-registers directly (SubReg;), then the spilling decision will
2006 Jan 20
11
Userstamp Plugin
I''m pleased to announce a new plugin for Rails: Userstamp. You can read my
blog post at http://www.delynnberry.com/articles/2006/01/20/userstamp-plugin
and/or read all about it at the perminant page
http://www.delynnberry.com/pages/userstamp. Any comments or suggestions for
improvement are much appreciated.
--
DeLynn Berry
delynn@gmail.com
http://www.delynnberry.com
A dump of the Readme
2006 Jun 14
1
Absolute URL from link_to?
What options do I need to provide to link_to so that it generates truly
absolute URLs (i.e. including protocol://host:port/path)? It seems that
even when I provide :host and :protocol arguments to url_for that it
suppresses these when they match the current request.
2018 May 22
4
Pasar palabras de una lista a una variable del dataframe
Buenas tardes,
Tengo una lista de 600 palabras. Quiero saber cuántas de esas palabras
aparecen en cada observación de mi variable "texto". La variable "texto"
es de tipo caracter. ¿Cómo lo haríais?
Muchas gracias.
2018 Jan 30
0
Disable spilling sub-registers in LLVM
I still think my answer applies that you have to modify storeRegToStackSlot()/loadRegFromStackSlot(). They decide how registers are spilled and reloaded. Nobody is stopping you from using super registers spills/reloads to implement spilling/reloading smaller registers there.
- Matthias
> On Jan 30, 2018, at 10:21 AM, ahmede <ahmede at ece.ubc.ca> wrote:
>
> Hi Quentin,
>
>
2018 May 23
2
Pasar palabras de una lista a una variable del dataframe
Muchas gracias Carlos,
Me da error al hacerlo. Mi variable donde quiero que localice las palabras
de la lista tiene más de una palabra, no se si puede ser por eso.
Gracias
El Mar, 22 de Mayo de 2018, 20:15, Carlos Ortega escribió:
> Hola,
>
> Aquí tienes un ejemplo (reproducible)...
>
> #-----------------------
>> # Generar nombres de mujer
>> library(randNames)
2015 Feb 03
2
[LLVMdev] Example for usage of LLVM/Clang/libclc
Hi,
My goal is to use Clang/LLVM/libclc to compile an OpenCL kernel and
eventually generate a PTX code. I already did this but I am not sure if the
PTX code I am generating is correct (is the one that is supposed to be
generated).
For example, currently,
In OpenCL : get_global_id(0) translates to
In LLVM : %call = tail call i32 @get_global_id(i32 0) which translates
to
In PTX:
2008 Jun 17
1
Plot point patterns
Hello!
I want to plot a multitype point pattern called "new" in package
spatstat. When I write plot(new) in the graphic window I can see a
strech rectangle with a point inside, not the point pattern.If I
write plot(new$x,new$y) the point pattern is plot ok.The problem
is that I want do the density plots, quadrat count, etc and in
these cases I can?t write density(new$x,new$y), I
2004 Aug 31
4
which distro for asterisk?
Hi
I want to play a bit with Asterisk. I currentlly install a new system
for that and I would like to get your recommendations regarding the
linux distro to use there.
This is NOT intended to become a general distro flame war. My favorite
distro is ******** and no argument that you flame will convince me here
(probably because I've heard it before).
However I would like to minimize the OS