similar to: More performance bencharmk data and graph for OCFS2 on IA32

I have optimized FLAC__fixed_compute_best_predictor_asm_ia32_mmx_cmov function and fixed bug when data_len == 0. Now the function is about 50% faster and flac -5 is about 5% faster on my box. I have tested it thoroughly, I think it can go to flac 1.0.4. -- Miroslav Lichvar -------------- next part -------------- --- src/libFLAC/ia32/fixed_asm.nasm.orig 2002-01-26 19:05:12.000000000 +0100 +++

Hello, I would like to announce the semi-optimized oc_state_loop_filter_frag_rows It gains like 7% speedup. Unfortunately it has some issues: 1) wont compile on 64bit (I will fix it later hopefully) 2) is not yet fully optimized (instruction stalls) Here are the results. CPU: Athlon, speed 1466.91 MHz (estimated) Counted CPU_CLK_UNHALTED events (Cycles outside of halt state) with a unit mask

Dear all, I wrote the following batch script on a iMac, and ran it on a linux mosix cluster. tu <- read.table("cage.mm5.tags.rna_lib.CAA-CAJ.tu-reshape.table") tu_reshaped <- t(reshape(tu[1:50,], direction="wide", timevar="tu", idvar=c("rna","lib"))) write.table(tu_reshaped, "cage.mm5.tags.rna_lib.CAA-CAJ.tu-reshaped.table")

Hi, First ,please excuse my poor English. Can someone help me on reading fortran binary object under R? I was trying to read mm5 data under R. However, I seem to stuck at reading fortran binary file storing met. data array. At the beginning, I used readBin() to read mm5 output directly with the following command. #mmout is a mmout file generated with mm5

Hello, Here is my first speedup patch. Like 10-11%. No IDCT yet. Please feel free to comment my code or even better think about improvements. :) I belive my routines are not so bad, maybe one day they will be even more faster. What needs to be optimized is the loop filter fuction. I have no ideas now how to do it. It does not leave much space for parallel stuff, copying memory from lot of

Hello, Here is my first speedup patch. Like 10-11%. No IDCT yet. Please feel free to comment my code or even better think about improvements. :) I belive my routines are not so bad, maybe one day they will be even more faster. What needs to be optimized is the loop filter fuction. I have no ideas now how to do it. It does not leave much space for parallel stuff, copying memory from lot of

Hi, I'm new to Theora and would like to propose several performance optimization using advanced instructions in x86 CPUs (SSE2-SSE4.2). There are several source files in \x86 and \x86_vc which developed using inline assembler. However this cause several maintenance problems: 1) Need to sync gcc & msvc versions 2) Only 32bit environment is supported 3) No support for newer than MMX

We are also thinking about locking for each read/write, but would its = overhead be too high? We have another idea that is extending the function of flock, lockf, = fcntl to distributed. So any application that need strict data consistent can do a lock = operation on the whole or part of the file. For ordinary application, maybe the current logic is enough. How about it? >-----Original

I've been attempting to calculate the predictions from a poisson glm object, along these lines: predict(foo.glm, type = "response") and predict(foo.glm, type = "response", se.fit = TRUE) foo.glm is arrived at this way: foo.glm <- glm(Insects ~ Dad * Mum + Location, offset = log(MM), family = "poisson", data = model.df) There are two

Hello group Im trying to plot 3d with scatterplot packages, i got error say " length(color) must be equal length(x) or 1 " may data has dimensions (lon,lat,lev,time) ,the time in month i want to calculate the monthly mean for the time how can i make that , is there any function doing that Thanks a lot ##load rgl package library(rgl) library(fields) library(ncdf)

On Oct 20, 2010, at 7:46 AM, Roland Scheidegger wrote: > On 20.10.2010 05:00, Jakob Stoklund Olesen wrote: >> Look in X86InstrControl.td. The call instructions are all prefixed >> by: >> >> let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, FP0, FP1, FP2, >> FP3, FP4, FP5, FP6, ST0, ST1, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, >> XMM0, XMM1, XMM2, XMM3,

On 20.10.2010 05:00, Jakob Stoklund Olesen wrote: > On Oct 19, 2010, at 6:37 PM, Roland Scheidegger wrote: > >> Thanks for giving it a look! >> >> On 19.10.2010 23:21, Jakob Stoklund Olesen wrote: >>> On Oct 19, 2010, at 11:40 AM, Roland Scheidegger wrote: >>> >>>> So I saw that the code is doing lots of register >>>>

(repost with right sender address) On 20.10.2010 18:13, Jakob Stoklund Olesen wrote: > On Oct 20, 2010, at 7:46 AM, Roland Scheidegger wrote: > >> On 20.10.2010 05:00, Jakob Stoklund Olesen wrote: >>> Look in X86InstrControl.td. The call instructions are all prefixed >>> by: >>> >>> let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, FP0, FP1,

On Oct 19, 2010, at 6:37 PM, Roland Scheidegger wrote: > Thanks for giving it a look! > > On 19.10.2010 23:21, Jakob Stoklund Olesen wrote: >> On Oct 19, 2010, at 11:40 AM, Roland Scheidegger wrote: >> >>> So I saw that the code is doing lots of register >>> spilling/reloading. Now I understand that due to calling >>> conventions, there's not

Hi r-help, I have some troubles reading fortran binary file(from mm5) in R. Here is what I have done. 1. Use a fortran subroutine to read this file in R. The subroutine is as the following. subroutine freadmm5(filenamet,out2d) integer iflag,var1,miy,mjx,mkz,mt,z,t character*4 crdt,corder character*24 chrdate character*9 cname,var character*25

On Monday 18 June 2007 19:02, Christopher Lamb wrote: > Take a look at getPhysicalRegisterRegClass( > const MRegisterInfo *MRI, > MVT::ValueType VT, > unsigned reg) > > in ScheduleDAG.cpp. Yuck. I was afraid of that. What is the ValueType needed for? Isn't the register id itself an indication of the ValueType it represents? Where I'm at I

On Sep 3, 2008, at 5:58 AM, Lang Hames wrote: > Hi LLVMers, > > I have finally sorted out licensing issues and found some time, so I'm > trying to port my PBQP register allocator to 2.4 in order to Nice! We would definitely welcome your contribution. > > contribute it (if you want it). I've run into a bug that has me > confused though. > > I'm currently

Hi LLVMers, I have finally sorted out licensing issues and found some time, so I'm trying to port my PBQP register allocator to 2.4 in order to contribute it (if you want it). I've run into a bug that has me confused though. I'm currently failing the following assertion: llc: VirtRegMap.cpp:1733: void<unnamed>::LocalSpiller::RewriteMBB(llvm::MachineBasicBlock&,

We cannot startup IA32/IA32pae unmodified linux guest OS. Booting 32bit VMX domain will stop at printing "ACPI: Unable to locate RSDP". Booting 32pae VMX domain will get a kernel panic. No abnormal info found in serial output. It''s interesting that sometime we can boot Windows 2003. Booting Windows SP1/SP2 Guest will crash with attached serial output. Bests Jeff

Hi, I''m trying to add PAE support to xen at the moment, and have some trouble with compiling the code at the moment. gcc complains about "initializer element is not computable at load time". The only explanation I have for that at the moment is that gcc has problems to deal with u64 (i.e. unsigned long long) calculations at compile time. Can anyone confirm or deny this?