similar to: Considering a major overhaul of the shuffle and boot functions

Displaying 20 results from an estimated 6000 matches similar to: "Considering a major overhaul of the shuffle and boot functions"

2009 May 03
1
Syslinux 3.80-pre7
I have just pushed out Syslinux 3.80-pre7. I am slightly concerned about putting this into the release tree at this point: I was working with some of the shuffler code, and found that the memory map handling was actually severely buggy on some of my test cases. Resolving that problem took rewriting most of syslinux_add_memmap(). However, against better judgement :) I decided to check in the
2015 Jan 25
4
[LLVMdev] RFB: Would like to flip the vector shuffle legality flag
I ran the benchmarking subset of test-suite on a btver2 machine and optimizing for btver2 (so enabling AVX codegen). I don't see anything outside of the noise with x86-experimental-vector-shuffle-legality=1. On Fri, Jan 23, 2015 at 5:19 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com > wrote: > Hi Chandler, > > On Fri, Jan 23, 2015 at 8:15 AM, Chandler Carruth
2015 Jan 23
5
[LLVMdev] RFB: Would like to flip the vector shuffle legality flag
Greetings LLVM hackers and x86 vector shufflers! I would like to flip on another chunk of the new vector shuffling, specifically the logic to mark ~all shuffles as "legal". This can be tested today with the flag "-x86-experimental-vector-shuffle-legality". I would essentially like to make this the default (by removing the "false" path). Doing this will allow me to
2016 Oct 28
1
Vector Shuffle chain lowering to X86 instructions simplification inconsistencies
Hi all, Attached herewith is a fairly simple LLVM file (shuffle.ll) with lots of vector shuffles. When I use llc with -O3 -mcpu=core-avx2 the first shuffle sequence containing types of 128 wide gets reduced a single shuffle, where as the second shuffle sequence containing types of 256 wide doesn't get reduced to a single shuffle instruction in the resulting X86 code (Shuffle.s attached).
2014 Sep 10
2
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
> On Sep 9, 2014, at 3:39 PM, Chandler Carruth <chandlerc at google.com> wrote: > > Awesome, thanks for all the information! > > See below: > > On Tue, Sep 9, 2014 at 6:13 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com <mailto:andrea.dibiagio at gmail.com>> wrote: > You have already mentioned how the new shuffle lowering is missing > some
2001 Sep 02
1
[PATCH] One-line shuffle fix
Looks like ogg123 has a thinko in the shuffling code; the attached patch (against today's CVS snapshot) fixes the problem. Please CC any replies to me; I'm not on the list. __________________________________________________ Do You Yahoo!? Get personalized email addresses from Yahoo! Mail http://personal.mail.yahoo.com/ <HR NOSHADE> <UL> <LI>X-unknown/X-unknown
2014 Sep 04
2
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
Greetings all, As you may have noticed, there is a new vector shuffle lowering path in the X86 backend. You can try it out with the '-x86-experimental-vector-shuffle-lowering' flag to llc, or '-mllvm -x86-experimental-vector-shuffle-lowering' to clang. Please test it out! There may be some correctness bugs, I'm still fuzz testing it to shake them out. But I expect fairly few
2014 Sep 19
4
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
Hi Chandler, I have tested the new shuffle lowering on a AMD Jaguar cpu (which is AVX but not AVX2). On this particular target, there is a delay when output data from an execution unit is used as input to another execution unit of a different cluster. For example, There are 6 executions units which are divided into 3 execution clusters of Float(FPM,FPA), Vector Integer (MMXA,MMXB,IMM), and Store
2010 Aug 04
2
[LLVMdev] x86 Vector Shuffle Patterns
I have a few questions about the new vector shuffle matching code in the x86 .td files. It's a big improvement over the old system and provides the context that code generation for AVX needs. This is great! I'm asking because I'm having some trouble converting some AVX patterns over to the new system. I'm getting this error from tblgen: VyPERM2F128PDirrmi: (set:isVoid
2014 Sep 30
2
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
Wow. Somehow, I forgot about vbroadcast and vpbroadcast. =[ Sorry about that. I'll fix those. On Fri, Sep 26, 2014 at 3:39 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com > wrote: > Hi Chandler, > > Here is another test. > > When looking at the AVX codegen, I noticed that, when using the new > shuffle lowering, we no longer emit a single vbroadcastss in the case
2008 Sep 30
0
[LLVMdev] Generalizing shuffle vector
Hi, I agree that the more general shufflevector is more useful. I narrowed the original proposal a little bit because of the concern for the implementation cost. However, the slightly narrowed definition will probably require falling backing to generate insert and extracts for complex masks so it is possible that there will be no extra cost in supporting the more general definition.
2005 Aug 14
4
3.10pre8 & ipod shuffle
Hello! I own an Ipod shuffle (512MB) and I am having trouble booting from it using syslinux 3.10pre8 (I have not tested older versions). I guess the Ipod shuffle works just like an ordinary USB key with a FAT32 partition so I have read http://syslinux.zytor.com/usbkey.php. My BIOS identifies it as a hard disk, so I hope I do not have to modify the geometry. Windows assigns the drive letter
2000 Dec 11
1
fixing shuffle in ogg123
Hi, There is a bug in the shuffle of ogg123 which was here at least until the CVS version of 3 days ago. Here's our fix: (it seems to be not perfectly equiprobable but at least fixes the old one which sometimes gives two times the same song and never the other song) -=-=-- --- vorbis-tools-1.0beta3/ogg123/ogg123.c.pix Sat Nov 4 01:23:21 2000 +++ vorbis-tools-1.0beta3/ogg123/ogg123.c Thu
2015 Nov 24
2
Hexagon and choosing of slots
> On Hexagon, the slot assignment is determined by the layout of the > instructions in memory. The order of the instructions in the packet does > not matter either in the IR, nor in the .s file, but it does when the > packet is encoded into the actual machine code. In LLVM, the Hexagon > shuffler orders the instructions just prior to encoding. > > Specifically, the
2015 Jan 29
0
[LLVMdev] RFB: Would like to flip the vector shuffle legality flag
On Wed, Jan 28, 2015 at 4:47 PM, Chandler Carruth <chandlerc at gmail.com> wrote: > > On Wed, Jan 28, 2015 at 4:05 PM, Ahmed Bougacha <ahmed.bougacha at gmail.com> > wrote: > >> Hi Chandler, >> >> I've been looking at the regressions Quentin mentioned, and filed a PR >> for the most egregious one: http://llvm.org/bugs/show_bug.cgi?id=22377
2008 Sep 30
0
[LLVMdev] Generalizing shuffle vector
Hi Mon Ping, Generalizing shufflevector would be great. I have an additional suggestion below. On 29-Sep-08, at 11:11 PM, Mon Ping Wang wrote: > I am proposing to extend the shuffle vector definition to be > <result> = shufflevector <n x <ty>> <v1>, <n x <ty>> <v2>, <m x i32> > <mask> ; yields <m x <ty>> > > The
2010 Oct 18
1
Randomly shuffle an array multiple times
Dear List, I have a table i have read into R: Name Yes/No John 0 Frank 1 Ann 0 James 1 Alex 1 etc - 800 different times. What i want to do is shuffle yes/no and randomly re-assign them to the name. I have used sample() and permute(), however there is no way to do this 1000 times. Furthermore, i want to copy the data into a excel spreadsheet in the same order as the data was input so i can
2015 Jan 30
0
[LLVMdev] RFB: Would like to flip the vector shuffle legality flag
I may get one or two in the next month, but not more than that. Focused on the pass manager for now. If none get there first, I'll eventually circle back though, so they won't rot forever. On Jan 30, 2015 11:21 AM, "Ahmed Bougacha" <ahmed.bougacha at gmail.com> wrote: > I filed a couple more, in case they're actually different issues: > -
2008 Sep 30
4
[LLVMdev] Generalizing shuffle vector
Hi, The current definition of shuffle vector is <result> = shufflevector <n x <ty>> <v1>, <n x <ty>> <v2>, <n x i32> <mask> ; yields <n x <ty>> The first two operands of a 'shufflevector' instruction are vectors with types that match each other and types that match the result of the instruction. The third
2014 Sep 20
2
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
After some adding some serious ninja-ry to the new shuffle lowering... On Fri, Sep 19, 2014 at 11:53 AM, Quentin Colombet <qcolombet at apple.com> wrote: > 2. none_useless_shuflle none > Instead of using a single move to materialize a zero extended constant > into a vector register, we explicitly zeroed a vector register and use a > shuffle. > ... this test case is fixed,