similar to: [PATCH 3/5] Make set_wrprotect() value safe

On Mon, Aug 15, 2005 at 04:00:39PM -0700, zach@vmware.com wrote: > Make the generic version of ptep_set_wrprotect a macro. This is good for > code uniformity, and fixes the build for architectures which include pgtable.h > through headers into assembly code, but do not define a ptep_set_wrprotect > function. This against the kernel coding style. In fact, we are usually doing

On Mon, Aug 15, 2005 at 04:00:39PM -0700, zach@vmware.com wrote: > Make the generic version of ptep_set_wrprotect a macro. This is good for > code uniformity, and fixes the build for architectures which include pgtable.h > through headers into assembly code, but do not define a ptep_set_wrprotect > function. This against the kernel coding style. In fact, we are usually doing

MMU code movement. Unfortunately, this one is a little bit more complicated than the rest. We have to override the default accessors that directly write to page table entries. Because of the 2/3-level PAE split in Linux, this turned out to be really ugly at first, but by allowing the sub-arch layer to override the definitions and keeping the native definitions in place, the code becomes much

MMU code movement. Unfortunately, this one is a little bit more complicated than the rest. We have to override the default accessors that directly write to page table entries. Because of the 2/3-level PAE split in Linux, this turned out to be really ugly at first, but by allowing the sub-arch layer to override the definitions and keeping the native definitions in place, the code becomes much

Implement lazy MMU update hooks which are SMP safe for both direct and shadow page tables. The idea is that PTE updates and page invalidations while in lazy mode can be batched into a single hypercall. We use this in VMI for shadow page table synchronization, and it is a win. It also can be used by PPC and for direct page tables on Xen. For SMP, the enter / leave must happen under protection

Change pte_clear_full to a more appropriately named pte_clear_not_present, allowing optimizations when not-present mapping changes need not be reflected in the hardware TLB for protected page table modes. There is also another case that can use it in the fremap code. Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> ---

Now that ptep_establish has a definition in PAE i386 3-level paging code, the only paging model which is insane enough to have multi-word hardware PTEs which are not efficient to set atomically, we can remove the ghost of set_pte_atomic from other architectures which falesly duplicated it, and remove all knowledge of it from the generic pgtable code. set_pte_atomic is now a private pte operator

We don't want to read PTEs directly like this after they have been modified, as a lazy MMU implementation of direct page tables may not have written the updated PTE back to memory yet. Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Cc: linux-mm@kvack.org --- mm/memory.c | 2 +- 1 file changed, 1 insertion(+), 1

From: Martin Schwidefsky <schwidefsky@de.ibm.com> From: Hubertus Franke <frankeh@watson.ibm.com> From: Himanshu Raj <rhim@cc.gatech.edu> [patch 9/9] Guest page hinting: full s390 support. s390 uses the milli-coded ESSA instruction to set the page state. The page state is formed by four guest page states called block usage states and three host page states called block content

From: Martin Schwidefsky <schwidefsky@de.ibm.com> From: Hubertus Franke <frankeh@watson.ibm.com> From: Himanshu Raj <rhim@cc.gatech.edu> [patch 9/9] Guest page hinting: full s390 support. s390 uses the milli-coded ESSA instruction to set the page state. The page state is formed by four guest page states called block usage states and three host page states called block content

With removal of lguest some of the paravirt functions are no longer needed. Remove them. Signed-off-by: Juergen Gross <jgross at suse.com> --- arch/x86/include/asm/desc.h | 3 +-- arch/x86/include/asm/paravirt.h | 37 ----------------------------------- arch/x86/include/asm/paravirt_types.h | 9 --------- arch/x86/include/asm/pgtable.h | 27

With removal of lguest some of the paravirt functions are no longer needed. Remove them. Signed-off-by: Juergen Gross <jgross at suse.com> --- arch/x86/include/asm/desc.h | 3 +-- arch/x86/include/asm/paravirt.h | 37 ----------------------------------- arch/x86/include/asm/paravirt_types.h | 9 --------- arch/x86/include/asm/pgtable.h | 27

Geert Uytterhoeven <geert at linux-m68k.org> writes: > On Mon, 13 Apr 2020, Geert Uytterhoeven wrote: >> Below is the list of build error/warning regressions/improvements in >> v5.7-rc1[1] compared to v5.6[2]. >> >> Summarized: >> - build errors: +132/-3 >> - build warnings: +257/-79 >> >> Happy fixing! ;-) >> >> Thanks to the

Add a pte_update_hook which notifies about pte changes that have been made without using the set_pte / clear_pte interfaces. This allows shadow mode hypervisors which do not trap on page table access to maintain synchronized shadows. It also turns out, there was one pte update in PAE mode that wasn't using any accessor interface at all for setting NX protection. Considering it is PAE

On Tue, Apr 14, 2020 at 08:23:32PM +1000, Michael Ellerman wrote: > Geert Uytterhoeven <geert at linux-m68k.org> writes: > > On Mon, 13 Apr 2020, Geert Uytterhoeven wrote: > >> Below is the list of build error/warning regressions/improvements in > >> v5.7-rc1[1] compared to v5.6[2]. > >> > >> Summarized: > >> - build errors: +132/-3 >

Hooks are provided for the mach-XXX subarchitecture at the time prior to a page being used as a page table at all levels, for PAE and non-PAE kernels. Note that in PAE mode, multiple PDP roots may exist on the same page with other data, so the root must be shadowed instead. This is not a performance issue, since PAE only uses 4 top level PDPEs. The hooks are: SetPagePTE(ppn) - indicates that a

Hooks are provided for the mach-XXX subarchitecture at the time prior to a page being used as a page table at all levels, for PAE and non-PAE kernels. Note that in PAE mode, multiple PDP roots may exist on the same page with other data, so the root must be shadowed instead. This is not a performance issue, since PAE only uses 4 top level PDPEs. The hooks are: SetPagePTE(ppn) - indicates that a

On Mon, 13 Apr 2020, Geert Uytterhoeven wrote: > Below is the list of build error/warning regressions/improvements in > v5.7-rc1[1] compared to v5.6[2]. > > Summarized: > - build errors: +132/-3 > - build warnings: +257/-79 > > Happy fixing! ;-) > > Thanks to the linux-next team for providing the build service. > > [1]

On Mon, 13 Apr 2020, Geert Uytterhoeven wrote: > Below is the list of build error/warning regressions/improvements in > v5.7-rc1[1] compared to v5.6[2]. > > Summarized: > - build errors: +132/-3 > - build warnings: +257/-79 > > Happy fixing! ;-) > > Thanks to the linux-next team for providing the build service. > > [1]

As usual, written and tested on 2.6.25.2 and made apply to the 2.6.18 tree without further testing. Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: head-2008-05-08/arch/x86_64/mm/pageattr-xen.c =================================================================== --- head-2008-05-08.orig/arch/x86_64/mm/pageattr-xen.c 2008-05-15 13:44:37.000000000 +0200 +++