similar to: [PATCH 6/6] i386 virtualization - Attempt to clean up pgtable code motion

Add one more MMU hook to the sub-arch layer. update_mmu_cache() - already defined. This is conveniently used to indicate NP->P transitions which should be reflected in an external TLB, and serves to indicate all points where the page tables must be synchronized. Required for lazy updates in shadow mode. There is only one case where an extra flush is needed, in the i386 specific page fault

Add one more MMU hook to the sub-arch layer. update_mmu_cache() - already defined. This is conveniently used to indicate NP->P transitions which should be reflected in an external TLB, and serves to indicate all points where the page tables must be synchronized. Required for lazy updates in shadow mode. There is only one case where an extra flush is needed, in the i386 specific page fault

MMU code movement. Unfortunately, this one is a little bit more complicated than the rest. We have to override the default accessors that directly write to page table entries. Because of the 2/3-level PAE split in Linux, this turned out to be really ugly at first, but by allowing the sub-arch layer to override the definitions and keeping the native definitions in place, the code becomes much

MMU code movement. Unfortunately, this one is a little bit more complicated than the rest. We have to override the default accessors that directly write to page table entries. Because of the 2/3-level PAE split in Linux, this turned out to be really ugly at first, but by allowing the sub-arch layer to override the definitions and keeping the native definitions in place, the code becomes much

On Mon, Aug 15, 2005 at 04:00:39PM -0700, zach@vmware.com wrote: > Make the generic version of ptep_set_wrprotect a macro. This is good for > code uniformity, and fixes the build for architectures which include pgtable.h > through headers into assembly code, but do not define a ptep_set_wrprotect > function. This against the kernel coding style. In fact, we are usually doing

On Mon, Aug 15, 2005 at 04:00:39PM -0700, zach@vmware.com wrote: > Make the generic version of ptep_set_wrprotect a macro. This is good for > code uniformity, and fixes the build for architectures which include pgtable.h > through headers into assembly code, but do not define a ptep_set_wrprotect > function. This against the kernel coding style. In fact, we are usually doing

Add a pte_update_hook which notifies about pte changes that have been made without using the set_pte / clear_pte interfaces. This allows shadow mode hypervisors which do not trap on page table access to maintain synchronized shadows. It also turns out, there was one pte update in PAE mode that wasn't using any accessor interface at all for setting NX protection. Considering it is PAE

I would like to host a phone meeting to discuss the plans for the xen sub-architecture of x86. Hopefully Chris can share his vision and we can agree on some next steps to getting this done and into the mainline kernel. From my understanding, it would be good if the "To" list could make it. If anyone believes others should attend, please let them know. Please let me know if you are

I would like to host a phone meeting to discuss the plans for the xen sub-architecture of x86. Hopefully Chris can share his vision and we can agree on some next steps to getting this done and into the mainline kernel. From my understanding, it would be good if the "To" list could make it. If anyone believes others should attend, please let them know. Please let me know if you are

A brave attempt to be rid of an unnecessary subarch hook and clean things up a bit. First, all subarches use IRQ-2 as a cascade IRQ. So do that in the common code. Second, there is no need for a pre_intr_init_hook. We can set up the interrupt gates at any time, as this doesn't touch any real hardware, just the processor gates. Now the subarch code still needs to setup the appropriate irq

A brave attempt to be rid of an unnecessary subarch hook and clean things up a bit. First, all subarches use IRQ-2 as a cascade IRQ. So do that in the common code. Second, there is no need for a pre_intr_init_hook. We can set up the interrupt gates at any time, as this doesn't touch any real hardware, just the processor gates. Now the subarch code still needs to setup the appropriate irq

Move header includes for the nopud / nopmd types to the location of the actual pte / pgd type definitions. This allows generic 4-level page type code to be written before the split 2/3 level page table headers are included. Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>

Move header includes for the nopud / nopmd types to the location of the actual pte / pgd type definitions. This allows generic 4-level page type code to be written before the split 2/3 level page table headers are included. Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>

Add comment and condense code to make use of native_local_ptep_get_and_clear function. Also, it turns out the 2-level and 3-level paging definitions were identical, so move the common definition into pgtable.h Signed-off-by: Zachary Amsden <zach@vmware.com> diff -r b3bbc1b5e085 include/asm-i386/pgtable-2level.h --- a/include/asm-i386/pgtable-2level.h Wed Apr 11 18:23:44 2007 -0700 +++

Move header includes for the nopud / nopmd types to the location of the actual pte / pgd type definitions. This allows generic 4-level page type code to be written before the split 2/3 level page table headers are included. Signed-off-by: Zachary Amsden <zach@vmware.com> diff -r 8233e2c507d3 include/asm-i386/page.h --- a/include/asm-i386/page.h Thu Oct 19 03:11:37 2006 -0700 +++

Move header includes for the nopud / nopmd types to the location of the actual pte / pgd type definitions. This allows generic 4-level page type code to be written before the split 2/3 level page table headers are included. Signed-off-by: Zachary Amsden <zach@vmware.com> diff -r 8233e2c507d3 include/asm-i386/page.h --- a/include/asm-i386/page.h Thu Oct 19 03:11:37 2006 -0700 +++

Add comment and condense code to make use of native_local_ptep_get_and_clear function. Also, it turns out the 2-level and 3-level paging definitions were identical, so move the common definition into pgtable.h Signed-off-by: Zachary Amsden <zach@vmware.com> diff -r b3bbc1b5e085 include/asm-i386/pgtable-2level.h --- a/include/asm-i386/pgtable-2level.h Wed Apr 11 18:23:44 2007 -0700 +++

Now that ptep_establish has a definition in PAE i386 3-level paging code, the only paging model which is insane enough to have multi-word hardware PTEs which are not efficient to set atomically, we can remove the ghost of set_pte_atomic from other architectures which falesly duplicated it, and remove all knowledge of it from the generic pgtable code. set_pte_atomic is now a private pte operator

The ptep_establish macro is only used on user-level PTEs, for P->P mapping changes. Since these always happen under protection of the pagetable lock, the strong synchronization of a 64-bit cmpxchg is not needed, in fact, not even a lock prefix needs to be used. We can simply instead clear the P-bit, followed by a normal set. The write ordering is still important to avoid the possibility of

When exiting from an address space, no special hypervisor notification of page table updates needs to occur; direct page table hypervisors, such as Xen, switch to another address space first (init_mm) and unprotects the page tables to avoid the cost of trapping to the hypervisor for each pte_clear. Shadow mode hypervisors, such as VMI and lhype don't need to do the extra work of calling