similar to: Memory corruption on Gallium window resize, diagnosed?

Hello, I have my work on the nv vpe video decoder in a functional state. In case you didn't know this decoder accelerates mpeg2 video at the idct/mc level. I have verified that it works on nv40 hardware. I believe it works on nv30 hardware (and maybe some earlier hardware), but I cannot verify since I have none. I will reply with patches against the kernel, drm, ddx and mesa for

This patch rewrites all the miptree layout and transfer code in the pre-NV50 Gallium drivers. The code is also unified among them and put in the nv04 directory. The current code is broken in several ways: 1. 3D textures are laid out first by face, then by level, which is incorrect 2. Cube maps should have 128-byte aligned faces 3. Swizzled textures have a strange alignment test that seems

Changes: - Fixed some nv##_miptree that were not converted to nv04_miptree. - Disable swizzling on non-RGBA 2D textures, since the current 2D code is mostly broken in those cases. A later patch will fix this. Thanks to Andrew Randrianasulu who reported this. This patch rewrites all the miptree layout and transfer code in the pre-NV50 Gallium drivers. The code is also unified among them and

Tegra K1 and later use a GPU that can be driven by the Nouveau driver. But the GPU is a pure render node and has no display engine, hence the scanout needs to happen on the Tegra display hardware. The GPU and the display engine each have a separate DRM device node exposed by the kernel. To make the setup appear as a single device, this driver instantiates a Nouveau screen with each instance of a

This patch series silences some unknown cap warnings and fixes up coding style (patch 1+4). The most important part of this series are the two patches in the middle. They rework the state_fb code, so that we are able to render to not 64 byte aligned targets, as this is the only real use-case for render temporaries this allows us to drop temp code completely and simplifies a lot

Adds H.264 and MPEG2 codec support via VP2, using firmware from the blob. Acceleration is supported at the bitstream level for H.264 and IDCT level for MPEG2. Known issues: - H.264 interlaced doesn't render properly - H.264 shows very occasional artifacts on a small fraction of videos - MPEG2 + VDPAU shows frequent but small artifacts, which aren't there when using XvMC on the same

https://bugs.freedesktop.org/show_bug.cgi?id=109330 Bug ID: 109330 Summary: GL_ALPHA_BITS set to non-zero with EGL_PLATFORM_GBM_MESA Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component:

- Added flush notify functions for NV30 and NV40. - NV30 and NV40 need testing. --- src/gallium/drivers/nouveau/nouveau_stateobj.h | 42 ++++++++++++++++++------ src/gallium/drivers/nv04/nv04_surface_2d.c | 9 +++-- src/gallium/drivers/nv30/nv30_context.c | 3 ++ src/gallium/drivers/nv30/nv30_context.h | 1 + src/gallium/drivers/nv30/nv30_state_emit.c | 10

On Sat, Jun 29, 2013 at 2:07 PM, Emil Velikov <emil.l.velikov at gmail.com> wrote: > Hi Ilia, > > On 27/06/13 12:26, Ilia Mirkin wrote: >> Adds H.264 and MPEG2 codec support via VP2, using firmware from the >> blob. Acceleration is supported at the bitstream level for H.264 and >> IDCT level for MPEG2. >> >> Known issues: >> - H.264 interlaced

https://bugs.freedesktop.org/show_bug.cgi?id=99464 Bug ID: 99464 Summary: openmw - Segfault with the nouveau ddx + DRI3 Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/nouveau Assignee:

Signed-off-by: Maarten Maathuis <madman2003 at gmail.com> --- src/gallium/drivers/nouveau/nouveau_stateobj.h | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/nouveau/nouveau_stateobj.h b/src/gallium/drivers/nouveau/nouveau_stateobj.h index b595405..28f483f 100644 --- a/src/gallium/drivers/nouveau/nouveau_stateobj.h +++

This logic is borrowed from the radeon code. The transfer logic will only get called for PIPE_BUFFER resources, so it shouldn't be necessary to worry about them becoming render targets. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- A user reported a ~30% FPS improvement with an earlier version of this patch in TF2, and no visual regressions in CS, all on a nv50 card. (Source

As it turns out, with the proprietary firmware, the VP3 and VP4 interfaces are identical. Furthermore, this is all already implemented for nvc0. So these patches (a) move the easily sharable bits of the nvc0 implementation into the nouveau directory, and then (b) implement the other parts in nv50. The non-shared parts are still largely copies, but there are some differences, not the least of which

Hi, please review the following patch! Thanks, Tobias Klausmann

v2: - change patch name to "nvc0: implement clear_buffer" - rename nvc0_clear_buffer_rgb32 -> nvc0_clear_buffer_cpu and make it work for all formats - remove superfluous fenciing in nvc0_clear_buffer_cpu - coding style fixes v3: - more coding style fixes - nvc0_clear_buffer() - don't mark the framebuffer dirty for if we don't touch the GPU Signed-off-by: Tobias

v2: change patch according to Ilia Mirkins review --- src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 151 ++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c index 6b7c30c..242924a 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c +++

* Sami Ketola: > They do not rely on Date header. Date header is not mandatory and also > it's not written on server side. It is written by the sender. Could you please elaborate on "Date header is not mandatory"? As far as the message format goes, "Date" and "From" are actually the two required headers in every message (see RFC 5322), so I am not quite

Normally for a log line containing the contents of a Message-Id, it is logged like the following Nov 29 11:41:27 xxx dovecot[211]: lmtp(lee)<30167><XXXXX>: sieve: msgid=<xxxx at example.net>: stored mail into mailbox 'Notifications' However, if there is CFWS other than a space, it changes the format of the log line (potentially making the logs harder to process - eg

- This avoids problematic "reloc'ed while mapped" messages and some associated corruption as well. Signed-off-by: Maarten Maathuis <madman2003 at gmail.com> --- src/gallium/drivers/nouveau/nouveau_screen.c | 21 +++++++++++++++++++++ src/gallium/drivers/nouveau/nouveau_screen.h | 3 +++ src/gallium/drivers/nouveau/nouveau_stateobj.h | 13 +++++++++++++

On Thu, Nov 27, 2014 at 11:39 AM, Thierry Reding <thierry.reding at gmail.com> wrote: > Tegra K1 and later use a GPU that can be driven by the Nouveau driver. > But the GPU is a pure render node and has no display engine, hence the > scanout needs to happen on the Tegra display hardware. The GPU and the > display engine each have a separate DRM device node exposed by the >