similar to: log transform a data frame

Thank you so much David, here is correction: d1=suppressWarnings(read.csv("/Users/anamaria/Downloads/B1.csv", stringsAsFactors=FALSE, header=TRUE)) d1$X <- NULL d2=as.matrix(sapply(d1, as.numeric)) pdf("~/graph.pdf") b<-barplot(d2, legend= c("SYCL", "CUDA"), beside= TRUE,las=2,cex.axis=0.7,cex.names=0.7,ylim=c(0,80), col=c("#9e9ac8",

Hi, I have a data frame like this: > dput(df) structure(list(ID = 1:8, Type = c("gmx mdrun -ntmpi 8 -ntomp 1 -s benchPEP.tpr -nsteps 10000 -resethway", "gmx mdrun -ntmpi 8 -ntomp 1 -s benchPEP.tpr -nsteps 10000 -resethway", "gmx mdrun -ntmpi 8 -s benchPEP.tpr -nsteps 4000 -resetstep 3000", "gmx mdrun -ntmpi 8 -s benchPEP.tpr -nsteps 4000 -resetstep

I have code like this: data <- read.csv("test1.csv", stringsAsFactors=FALSE, header=TRUE) # Graph myplot=ggplot(data, aes(fill=condition, y=value, x=condition)) + geom_bar(position="dodge", stat="identity", width=0.5) + scale_fill_manual(values=c("#7b3294", "#c2a5cf", "#a6dba0", "#008837"))+

Hi, Everyone: Can anyone let me know the default NEON registers llvm going to use with armv7 devices? For example, d10 and d11 are treated as default zero? I am using Xcode5 + llvm and I got a case that compiler will generate neon codes " vst.8 {d10, d11}, [r1] " from C codes: "int aMV[4]; ...... aMV[0] = aMV[1] = aMV[2] = aMV[3] = 0; " and I

Dear Admin, I will appreciate if you advise me an effective way to write the following R code including nested for loops. I cannot do it by using expand.grid function because it results with memory allocation problems. Thanks for your time and consideration. for(d1 in 0:n){ for(d2 in 0:n){ for(d3 in 0:n){ for(d4 in 0:n){ for(d5 in 0:n){ for(d6 in 0:n){ for(d7 in 0:n){ for(d8 in 0:n){ for(d9 in

A mi también me funciona para los dos casos: > dat <- read.csv("d11-16.csv", header=FALSE, sep=",", dec=".", skip=11, nrows=1) > dat V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 1 masa total en µg 30.04633 ug PEAKS MUY PEQUENOS NA NA NA NA NA NA NA > dat18 <- read.csv("d11-18.csv", header=FALSE,

Hi, I have Holiday table. the fileds are id,holiday_date,description. i added new records and list them also. when i listed all the records in the database are listed but i want to list only one particular year records. my holiday_list.rhtml page is as follows <%= stylesheet_link_tag "common", :media => "all" %> <%= error_messages_for ''holiday''

Thanks. This is making a lot more sense now and it's looking like this issue isn't Mips specific. Here's the IR dump before simple register coalescing (note: I've patched the IR printer to print the contents of the regmask): 4480B %vreg260<def> = LDC1 %vreg253, <cp#3>[TF=6]; mem:LD8[ConstantPool] AFGR64:%vreg260 GPR32:%vreg253 4496B %vreg261<def> = FMUL_D32

Hi all, We'd like to some SYCL tests to LLVM's test suite. The SYCL support in the LLVM repo is still very much a work-in-progress, but since the test-suite is supposed to be able to support compilers other than clang, I thought it would be reasonable to start adding the tests there now, disabled by default, rather than maintaining a fork of the test-suite repo until SYCL support is fully

Thanks, Johannes! It would be nice to have some additional infrastructure to control execution of tests that have special resource requirements like this. We've seen some problems in our internal testing with parallel test execution causing system gridlock. Having a common way to address that would be great. One reason I thought separate SYCL folders (either at the top level or elsewhere in

Hi , I am trying to get some estimator based on lognormal distribution when we have left,interval, and right censored data. Since, there is now avalible pakage in R can help me in this, I had to write my own code using Newton Raphson method which requires first and second derivative of log likelihood but my problem after runing the code is the estimators were too high. with this email ,I provide

Hi mailinglist members, I’m actually working on a time series prediction and my current approach is to decompose the series first into a trend, a seasonal component and a remainder. Therefore I’m using the stl() function. But I’m wondering how to get the single components in order to predict the particular fitted series’. This code snippet illustrates my problem: series <-

Hi Johannes, The structure you suggested makes sense to me. Vladimir Lazarev has been working on moving some end-to-end tests out of the source tree (in the intel/llvm GitHub branch where the parts of our SYCL development that aren’t ready to be included in the main LLVM repo are being shared). He has a local working copy that can run the tests with various hardware and device runtimes. The last

That’s a good question. I’m afraid I don’t know how/if that’s controlled in these tests. From: Johannes Doerfert <johannesdoerfert at gmail.com> Sent: Monday, June 08, 2020 3:05 PM To: Kaylor, Andrew <andrew.kaylor at intel.com>; Lazarev, Vladimir <vladimir.lazarev at intel.com> Cc: LLVM Developers <llvm-dev at lists.llvm.org>; bhomerding at anl.gov; Finkel, Hal J.

Yeah:) I''d like to work on this. Here are my first observations: - We need to call vdev_op_asize method with additonal ''offset'' argument, - We need to move data to new disk starting from the very begining, so we can''t reuse scrub/resilver code which does tree-walk through the data. Below you can see how I imagine to extend RAIDZ. Here is the legend:

Estimada comunidad, estoy extrayendo una linea de texto desde varios archivos (unos 200) de esta manera: dat <- read.csv(filenames[i], header=FALSE, sep=",", dec=".", skip=11, nrows=1) pero al tratar de leer esa linea desde el archivo numero 54 obtengo el siguiente error: Error in type.convert(data[[i]], as.is = as.is[i], dec = dec, na.strings = character(0L)) :

Fabian, > here are the definitions of these register classes: > > // Data register class > def DR : RegisterClass<"TriCore", [i32], 32, > (add D0, D1, D2, D3, D4, D5, D6, D7, > D8, D9, D10, D11, D12, D13, D14, D15)>; > > // Extended-size data register class > def ER :

2012/8/21 Anton Korobeynikov <anton at korobeynikov.info>: >> This isn't really my area of expertise, but I think you're messing up >> your RegisterClass definition. Look at how ARM defines DTriple. > DTriple is untyped :) , because we do not have any valut type which > defines 3xi64. > However, the paired register needs to have type. > > Fabian, what are

Hi Karel, I understand this patch has already been merged (to 3.0), so don't take my question as stopping the merge to head, I'm just making sure I got it right... The rest looks correct. + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, + CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, + CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22,

Hi, We have a number of 4200''s setup using a combination of an SVM 4 way mirror and a ZFS raidz stripe. Each disk (of 4) is divided up like this / 6GB UFS s0 Swap 8GB s1 /var 6GB UFS s3 Metadb 50MB UFS s4 /data 48GB ZFS s5 For SVM we do a 4 way mirror on /,swap, and /var So we have 3 SVM mirrors d0=root (sub mirrors d10, d20, d30, d40) d1=swap (sub mirrors d11, d21,d31,d41)