similar to: Optimised qmf_synth and iir_mem16

On 12/13/07, Jean-Marc Valin <jean-marc.valin@usherbrooke.ca> wrote: > Did you test what happens if you only enable arm4 assembly? Sure. I tested with "--enable-arm4-asm" and there was no difference. > Also, if you can do some investigation, it would be useful to check what bit > of assembly is causing the crash. Can you disable one at a time and check? ok. I'll try

The attached patches are against the v0.114 release and cover some of the tweaks I made while playing about testing ARM and Thumb support. Please review and consider applying. Even with the patches, ARM dynamic linking doesn't seem to work and the Thumb test applications seem to have shaken out a Thumb bug in the 2.4.21-rmk2 kernel which I'm still trying to track down. Still more fun to

Hi Bjorn, could you file a bug on llvm.org/bugs and cc me on it. Thanks, Arnold > So it appears that also the ARM backend has a big problems with sign-extending loads. > > I've compiled the following loop > > short in[]; > int out[]; > int value; > > for (i = 0; i < nr; i++) { > value = in[i]; > if (value>2047) >

-----Original Message----- From: Jean-Marc Valin <jean-marc.valin at usherbrooke.ca> To: ??????? ??????? <altersoft at mail.ru> Date: Sat, 02 Aug 2008 07:54:34 -0400 Subject: Re: [Speex-dev] fir_mem16,iir_mem16 and filter_mem16 optimisations > > ??????? ??????? a ?crit : > > I have some questions about that functions: fir_mem16, iir_mem16 and filter_mem16. > >

Hi! I have some questions about that functions: fir_mem16, iir_mem16 and filter_mem16. Filtering is very slow on TI DSP, and i want to optimise it. Can somebody give me formulas which discribe work of this filters? Or any suggestions about how to transform code for better performance. I going to implement this functions in assembler, but it is hard to do without full understanding how functions

Dear Sirs, I would be interested to hear your views on whether SPEEX could be made to run fast on a DSPIC33 by the following strategy: Make iir_mem16() (for example) purely 16 bit by restricting the number of bits in the signal to say 10 using SATURATE and then making the LPC co-efficients just 6 bits. At present (with standard code) the encode function is taking about 140ms which is seven

done, bug 15057, hope I submitted it correctly ... On 23 Jan 2013, at 22:29, Arnold Schwaighofer <aschwaighofer at apple.com> wrote: > Hi Bjorn, > > could you file a bug on llvm.org/bugs and cc me on it. > > Thanks, > Arnold > > >> So it appears that also the ARM backend has a big problems with sign-extending loads. >> >> I've compiled the

arm: implement exception and hypercall entries. xen/arch/arm/xen/Makefile | 3 + xen/arch/arm/xen/asm-offsets.c | 61 ++++++++ xen/arch/arm/xen/entry.S | 596 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/xen/hypercalls.S | 67 +++++++++ xen/arch/arm/xen/physdev.c | 41 +++++ 5 files changed, 768 insertions(+), 0

- Use MAC16_16 macros instead of (sum += a*b) and unroll a loop by 2. It increase performance when using optimized macros (ex: ARMv5E). A possible side effect of loop unroll is that i don't check for odd length here. - Add NEON version of FIR filter and autocorr -- Aur?lien Zanelli Parrot SA 174, quai de Jemmapes 75010 Paris France -------------- next part -------------- diff --git

Please ignore my previous mail and patch, there is a new version :). Patch changes are: - Use MAC16_16 macros instead of (sum += a*b) and unroll a loop by 2. It increase performance when using optimized macros (ex: ARMv5E). A possible side effect of loop unroll is that i don't check for odd length here. - Add NEON version of FIR filter and autocorr - Add a section in autoconf in order to

[Please keep r-help in the cc: list] I don't quite know how to interpret the difference between specifying effort as an offset vs. as weights; I would have to spend more time thinking about it/working through it than I have available at the moment. I don't know that specifying effort as weights is *wrong*, but I don't know that it's right or what it is doing: if I were

On some systems (alpha), tick marks don't appear on plots. The easiest way to see the problem is something like: > plot(0:1,axes=FALSE) > axis(1,1:2) The problem is in X11_Line(...) from .../src/unix/devX11.c, which is so short I've included the whole function below: static void X11_Line(double x1, double y1, double x2, double y2, int coords, DevDesc *dd) {

On Wed, Feb 9, 2011 at 5:02 AM, Vasiliy Korchagin <vasiliy.korchagin at gmail.com> wrote: > Hi, > > llvm emits code for "memcpy" on ARM as consecutive ldr/str commands, and Hmm, this happens elsewhere as well (x86?). Perhaps what we need is a switch to disable memset/memcpy lowering? > further combines them into ldm/stm with special pass after register >

> -----Message d'origine----- > De : Jean-Marc Valin [mailto:jean-marc.valin at usherbrooke.ca] > Envoy? : dimanche, 14. juin 2009 20:46 > ? : Stephane Lesage > Cc : speex-dev at xiph.org > Objet : Re: [Speex-dev] Resampler saturation > > Just to make sure I understand, the two patches you sent are > two different ways to fix the problem, with the only >

Can someone explain why I am getting the following error: in the r code below? Error in solve.default(diag(2) + ((1/currvar) * (XX1 %*% t(XX1)))) : system is computationally singular: reciprocal condition number = 0 In addition: There were 50 or more warnings (use warnings() to see the first 50) The R code is part of a bigger program. ##sample from full conditional

Hi, llvm emits code for "memcpy" on ARM as consecutive ldr/str commands, and further combines them into ldm/stm with special pass after register allocation. But ldm/stm commands require registers to go in ascending order, what is often not so after regalloc, therefore some str/ldr commands. For example such code: struct Foo {int a, b, c, d; } void CopyStruct(struct Foo *a, struct

R-users E-mail: r-help@r-project.org Hi! R-users. http://finzi.psych.upenn.edu/R/library/mvpart/html/xpred.rpart.html says: data(car.test.frame) fit <- rpart(Mileage ~ Weight, car.test.frame) xmat <- xpred.rpart(fit) xerr <- (xmat - car.test.frame$Mileage)^2 apply(xerr, 2, sum) # cross-validated error estimate # approx same result as rel. error from printcp(fit) apply(xerr, 2,

Hi All, I am trying to convert the following piece of matlab code to R: XX1 = sum(w(:,ones(1,N1)).*X1.*X1,1); #square the elements of X1, weight it and repeat this vector N1 times XX2 = sum(w(:,ones(1,N2)).*X2.*X2,1); #square the elements of X2, weigh and repeat this vector N2 times X1X2 = (w(:,ones(1,N1)).*X1)'*X2; #get the weighted 'covariance'

(readding cc llvmdev) On Feb 24, 2012, at 11:46 AM, محمد ﻋﻤﺮ ﺩﻫﻠﻮﻯ <omerbeg at gmail.com> wrote: > > > otherwise how are the machine instructions being accessed/matched for instruction selection ? > > > > Have a look at the code in SelectionDAGISel. > > > I am looking at the ARM backend. > In specific, the instruction selection. > In Select(N),

-fno-builtin is the flag you want. deep On Wed, Feb 9, 2011 at 10:18 PM, Корчагин Василий <vasiliy.korchagin at gmail.com> wrote: > 09.02.2011 18:57, Jason Kim пишет: >> On Wed, Feb 9, 2011 at 5:02 AM, Vasiliy Korchagin >> <vasiliy.korchagin at gmail.com>  wrote: >>> Hi, >>> >>> llvm emits code for "memcpy" on ARM as consecutive