similar to: new assembler port

> I suggest that you start by looking at 8kbps, complexity 0. Actually, I strongly recommand *against* using complexity 0, unless you're really desperate for a few MIPS. The complexity reduction compared to 1 is small, but the loss in quality can be significant. > I (and others) > are running that on a TI C55xx DSP, and it runs a little under 30 MIPs when > I last checked, with

> I'm trying to use speex for implementing a VoIP demo application using > linphone > on an embedded system. At the moment I'm not really able to do real time > encoding, > and thinking about making an assembler port for speex to the AVR32 > architecture. > The AVR32 is a new hybrid MCU/DSP fixed point processor running at 120Mhz > in > my application. >

Greetings everyone, I'm trying to compile asterisk for an AVR32 (Atmel NGW100). Buildroot for AVR32 already has the asterisk package, though it has bugs. Firstly it tries to apply a patch for 1.2 on a 1.6, but deleting the contents of the patch file did the trick. Now, the problem is making asterisk. The first error is because asterisk needed to be ./configure:ed. Trying to just do

Greetings, I've just started porting speex to a TI C5509 DSP. It doesn't look like it's going to be too painful, but there are a couple of quirks about the C5x. 1) chars are 16 bits because memory addresses are for 16bit words 2) ints and short are also 16 bits (so sizeof(char) = sizeof(short) = sizeof(int) = 1) 3) the c5x is essentially big endian My plan is to change int and

Jean-Marc Valin wrote: >Hi Jamey, > >Really cool to see Speex being ported to the C55xx and I'd be glad to >integrate the changes required in Speex (and the style's fine with me). > > I have the encoder and decoder running now and have verified that the encoder is bit-exact wrt to the fixed-point code running on x86 for the same 30-second audio sample. Encode and

Hello, I am interested to use Speex but need to know If I can use it under our project's constraint. We need to use a low cost micro controller on a very small PCB. This means there's no space for an external DSP unit. Can someone tell me if using an AVR32 (Atmel uc) which has a floating point calculation unit and DSP instruction set and running at ~50Mhz for a narrow band

Hello, would it be possible to update config.sub and config.guess to the latest versions (or at least version from automake-1.13.1) in order to support new architectures based on the ARM 64 bit CPU? Patch: http://plautrba.fedorapeople.org/openssh/openssh-latest-config.sub-config.guess.patch Related Fedora bug: https://bugzilla.redhat.com/show_bug.cgi?id=926284 Thanks, Petr

> I have a client who might well make use of an AVR32 port, but I suspect > that machine is very different than the one you are currently examining. I have not looked at AVR32 closely but my understanding is that it is a new architecture that shares a substring with AVR for marketing reasons. John

I have a client who might well make use of an AVR32 port, but I suspect that machine is very different than the one you are currently examining. shap On Mon, 2008-05-19 at 12:38 -0600, John Regehr wrote: > Anyone else interested in an AVR backend? > > If so, for what members of the AVR family? If we do a port, likely it'll > support only the ATmegas. > > John >

Hi, On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction sequence it is now. I'm not sure if adding RBIT to ARMISD and doing this optimization in the legalize pass is the best option, but the only better way I could think of doing it was to add a bitreverse intrinsic to llvm ir, which itself might not be the best option since bitreverse probably isn't too common. Other

On 15 Jan 2010, at 18:03, Chris Lattner wrote: > On Jan 14, 2010, at 10:13 PM, David Conrad wrote: > >> Other targets that I know of that could potentially benefit from >> this optimization being global (that have a clz and bitreverse >> instruction but not ctz) are AVR32 and C64x, neither of which llvm >> has backends for yet. > > When/if another

On Jan 14, 2010, at 10:13 PM, David Conrad wrote: > Hi, > > On ARMv6T2 this turns cttz into rbit, clz instead of the 4 > instruction sequence it is now. > > I'm not sure if adding RBIT to ARMISD and doing this optimization in > the legalize pass is the best option, but the only better way I > could think of doing it was to add a bitreverse intrinsic to llvm

Gents, My TI C55xx complier is complaining about (in opus_encoder.c, opus_encode()): st->silk_mode.payloadSize_ms = 1000 * frame_size / st->Fs; where .payloadSize_ms is opus_int, frame_size is an int, and Fs is a long. Should one of these be cast differently? Thx, MikeH -------------- next part -------------- An HTML attachment was scrubbed... URL:

Dear all, I'm Arun, new in this group. and newbie in Linux also. I am working on linphone and I want to compile linphone, but before that I want to compile speex-1.1.10 for uClinux using bfin-gcc. I used these three files : uClinux-dist-2005R3.tar.bz2 bfin-gcc-3.4-2005R3.1.tar.gz speex-1.1.10.tar I sucessfully compiled and installed bfin-gcc, and

From: Matt Fleming <matt at console-pimps.org> Uncovered a bug in avr32 signal handling, might come handy in testing other archs signal. Signed-off-by: Matt Fleming <matt at console-pimps.org> Signed-off-by: maximilian attems <max at stro.at> --- Seen on lmkl, any objections to add your test to klibc: http://git.kernel.org/?p=libs/klibc/klibc.git;a=summary We know archs were

Anyone else interested in an AVR backend? If so, for what members of the AVR family? If we do a port, likely it'll support only the ATmegas. John

No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield in sched.h. Suggested-by: Russell King <linux at armlinux.org.uk> Signed-off-by: Christian Borntraeger <borntraeger at de.ibm.com> --- arch/alpha/include/asm/processor.h | 1 - arch/arc/include/asm/processor.h

No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield in sched.h. Suggested-by: Russell King <linux at armlinux.org.uk> Signed-off-by: Christian Borntraeger <borntraeger at de.ibm.com> --- arch/alpha/include/asm/processor.h | 1 - arch/arc/include/asm/processor.h

Hi, I am writing a backend for the Blackfin processor from Analog Devices. I just started so I still have a lot to learn about the code generator. So far, I can compile test/CodeGen/Generic/BasicInstrs.ll correctly, but that is about it. The Blackfin 32-bit registers divide naturally into several classes. I have modelled these register classes without knowing anything about what the code

Robin Getz a ?crit : >> As I told you, bank is a reserved keyword in Analog Devices compiler for >> Blackfin architecture. > > This seems lame, and maybe you need to change the header files inside VDSP++. > (This is pretty common for VDSP users to do when name space clashes occur > with open source software). > > Poking at the VDSP docs, says that it uses bank()