similar to: Re: sigsegv in _mm_load_ups (linux/gcc 3.x)

> I've seen the exact same in my version (mingw on win32), and the problem > was that the stack was misaligned when entering the function, so the temp > registers weren't at 16-byte boundries. That's a possibility. It's easy to check by printing the address of the variables. I know that gcc 3.3 had some alignment issues with _m128 that were supposed to be fixed in

Hi Jean-Marc, Hi Jim, I have also seen some problems with the 1.1.8 release on the C55x. So far I have boiled down the issues to the following: 1) We need our own "fixed_xx.h" header file. I don't know why, and haven't had time to investigate, but there is a definite improvement when I use the attached fixed_c55x.h file which has turned all the maths into inline functions.

Building svn 10958 on amd64, gcc-4.1: gcc -DHAVE_CONFIG_H -I. -I. -I.. -I../include -I../include -I.. -I/usr/include -O2 -fPIC -funswitch-loops -fvisibility-inlines-hidden -march=k8 -ftree-vectorize -pipe -mfpmath=sse -O3 -msse -MT filters.lo -MD -MP -MF .deps/filters.Tpo -c filters.c -fPIC -DPIC -o .libs/filters.o cc1: warning: command line option "-fvisibility-inlines-hidden" is

>> I've seen the exact same in my version (mingw on win32), and the problem >> was that the stack was misaligned when entering the function, so the temp >> registers weren't at 16-byte boundries. > > That's a possibility. It's easy to check by printing the address of the > variables. I know that gcc 3.3 had some alignment issues with _m128 that > were

I'm not sure what you're trying to achieve here, but SSE and fixed-point are mutually exclusive. Jean-Marc On Sat, 2006-02-25 at 19:02 -0500, sean darcy wrote: > Building svn 10958 on amd64, gcc-4.1: > > gcc -DHAVE_CONFIG_H -I. -I. -I.. -I../include -I../include -I.. > -I/usr/include -O2 -fPIC -funswitch-loops -fvisibility-inlines-hidden > -march=k8 -ftree-vectorize

All, Attached is a patch that does two things. First it makes the use of the current SSE code a run time option through the use of speex_decoder_ctl() and speex_encoder_ctl It does this twofold. First there is a modification to the configure.in script which introduces a check based upon platform. It will compile in the sse assembly if you are on an i?86 based platform by making a

I'm trying to make a design decision between a TI 6416 or DM642 (fixed point) and 6713 (floating point) platform. The application is a 32 channel speech encoder. (CBR only, 8khz, 8kbps) To get a feel for the computational load, I am running 1 second (50 frames) of voice through the encoder. My profile of the 6416 indicates I'm at 27.4M cycles/channel. I need to get below 720Mhz/32

I am studying the speex 1.0.5 C source code ,but i feel it is hard to understand the code ,especially the ltp.c and filters.c file. may you tell me the detail algorithm or the more detail notation of the source code of this two file.including below functions void open_loop_nbest_pitch(float *sw, int start, int end, int len, int *pitch, float *gain, int N, char *stack); float

Hi, I've tried the same configure options on my system and it doesn't crash. I have the same glibc and gcc 3.3.2 (can you see if a newer gcc works?). Also, could you explore a bit with different options so we can narrow it down a bit. For example, does it work with the default CFLAGS or without --vbr or --dtx. Last thing, maybe it's the file. If so, please send me the smallest sample

System: Linux 2.4.25, glibc-2.3.2, gcc-3.2.3 (weird palindrome there), on a Williamette core Pentium 4 (1.6Ghz) system. I've tried both speex 1.1.5 release, and the current CVS (which self-IDs as 1.1.4), and the result is the same. I suspect some funk in the use of the SSE intrinsics macros. Backtrace: #0 0x40024594 in filter_mem2_10 (x=0x805f31c, _num=0x8061fb8, _den=0x8061fe4,

Le jeu 15/01/2004 à 15:30, Daniel Vogel a écrit : > Unrelated, but please use SSE/MMX/... intrinsics on Windows instead of using > inline assembly so you also get the speed benefit on Win64. OK, so here's a first start. I've translated to intrinsics the asm I sent 1-2 days ago. The result is about 5% slower than the pure asm approach, so it's not too bad (SSE asm is 2x faster

Tom, Thorvald, Could one of you submit the details to the gcc bugzilla so it gets fixed? BTW, is 4.0 affected? Jean-Marc Le vendredi 06 janvier 2006 ? 17:13 -0800, Tom Harper a ?crit : > Thorvald, > > re: > At 03:18 AM 1/6/2006, Thorvald Natvig wrote: > >I just checked it in the debugger, and this was with gcc 3.4.4 (mingw)... > >And the addresses were not properly

Thorvald, re: At 03:18 AM 1/6/2006, Thorvald Natvig wrote: >I just checked it in the debugger, and this was with gcc 3.4.4 (mingw)... >And the addresses were not properly aligned :( From a bit of googling, >this seems to be a thread problem, as the gcc just maintains 16-byte >alignment of the stack -- if the start function of the thread had >misaligned stack, the misalignment

Hy, I'm writing a application using speex. This app have two threads one is encoding the other one decoding using speex. I dont know why but I got segfault on some systems. If I juste take off one of the thread like encoding and lauchin the decoding part in a thread and the application is still segfaulting. But if I just launch the decoding process with out a thread every thing is going

Jean-Marc, Good catch on the debug mode. After compiling the same code in release mode it does appear to be using all the registers correctly. Give us a few days to integrate our run-time flags into 1.1.4 and I will let you know how are testing turns out. Aron Rosenberg SightSpeed At 08:54 PM 1/21/2004, you wrote: > > 1. Compile Error with regular mode (FIXED_POINT undefined)

> There is a big difference between SSE and SSEFP. The SSEFP means > that the CPU supports the xmm registers. All Intel chips with SSE support > do, however no current 32 bit AMD chips support the XMM registers. They > will support the SSE instructions but not those registers. You are right > about the SSE2 not being used. I'm still not sure I get it. On an Athlon

Hi Jean Marc and List, So I have started finally fiddling around with Ultra-wideband mode. It appears to be very similar in operation to Wide mode, except that when peering into the packet structure it looks like (and these are kind of questions as much as statements here): 1. update rate 0 is not used in UWB- only 1-4? 2. The total bits used for each UWB update rate seem to be as follows:

Not a big deal, but the "<http://xiph.org/svn.html>Subversion Access" link on http://www.speex.org/download.html page should probably point to: http://www.xiph.org/svn/ rather than: http://xiph.org/svn.html Tom ______________________________________________ Tom Harper Lead Software Engineer SightSpeed - <http://www.sightspeed.com/>http://www.sightspeed.com/ 918 Parker

Congrats Jean Marc, Just heard you got a new google assistant for the Ghost project! Tom ______________________________________________ Tom Harper Lead Software Engineer SightSpeed - <http://www.sightspeed.com/>http://www.sightspeed.com/ 918 Parker St, Suite A14 Berkeley, CA 94710 Email: tharper@sightspeed.com Phone: 510-665-2920 Fax: 510-649-9569 My SightSpeed Video Link:

Jean-Marc, So I saw in the latest code that the vad in the preprocessor is gone/going to be re-written. Is there a plan as far as this goes? Just wondering as the current one seems to work pretty well. Thanks! Tom ______________________________________________ Tom Harper Lead Software Engineer SightSpeed - <http://www.sightspeed.com/>http://www.sightspeed.com/ 918 Parker St, Suite A14