similar to: Updated MIPs and memory requirements for TI c54x or c55 DSPs

Hi, Just a couple tips to reduce complexity. First, I think you'd get a good speedup by enabling the PRECISION16 switch (if it's not done already). This (very) slightly reduces quality, but means you convert a lot of "emulated" 16x32 multiplications into 16x16. There are also several routines that would benefit from platform-specific optimizations. There are already

The attached file contains build files for TI's Code Composer Studio (CCS) for the C54x, C55x, and C6x DSPs. I had intended to post this a couple of months ago, but it took a long time to get around to doing the little bit of cleanup required. This is a file I/O loopback application suitable for running with the CCS simulators, for evaluating memory and MIPs requirements for these

Hi Jim, Thank for the patch. I'll apply it when I have a few minutes. If I haven't done so after a few weeks, please send it again. I'm in the process of relocating to Australia, so everything's a bit of a mess around here. Also, please post the c5X-specific files to the list (.cmd, .pjt, ...) so they'll be archived. Last thing, I see you defined spx_word64_t as long long for

Hi Jim, > Build 11169 in SVN works correctly. Good. I'll try not to forget the EXTEND32 from now on. > I have attached a zip file (renamed > .txt) with a patch to bits.c to make the byteswapping for TI DSPs > consistent. Seems like unzip can't read it. Either it's in an unknown format or the file got corrupted. Could simply send as multiple (uncompressed)

Jean-Marc Valin wrote: > I don't know all the details, but here's a (partial) list of archs on > which I've heard of Speex running. I'm sure there are others (especially > the float version should really run on any chip with an FPU). > > float: > x86/x86-64 (SSE assembly optimizations provided) > PowerPC > SPARC I've had floating decoding running on a

John, > I can see that there has been some effort to compile the SPEEX codec to operate on the > TI c54x and c55x DSPs and I am wondering if anyone would be able to update the > mailing list with their current MIPs and Memory resource requirements for their c54x > and/or c55x compilation? The only estimate I was able to find in the mailing list archive > was 42MIPs but I'm

Jean-Marc, I have attached a small patch with modifications to arch.h, bits.c, and misc.c. This contains the few mods remaining to support the various fixed point TI DSPs after the work that you did at the end of May (thank you for this). arch.h: Add switch for compilers not supporting "long long" (C55x does, C54x and older C64x does not) bits.c: Allow external definition for max

> >I fixed it in svn. Could you check that? > > Now all platforms match again. Note that the measured SNR for this test > sample is lower than with the broken code (10.87 vs 11.10), but of course > this is no way to judge the real quality. SNR, especially on a single sample, can be very misleading. Yet, could you just check that the DSP results match what you get on a PC?

> You found it. The SHL32 (not SHR32) line fixes the problem. It must be > doing a 16-bit shift, then extending the result (which is reasonable). As > it happens, that it the same macro which gave us trouble last May > (25th/26th), when the C55 build was more subtlely broken. Yes, that's what I finally remembered. I think I've fixed all occurrences (by adding EXTEND32)

Stuart, Jean-Marc, >> 1) We need our own "fixed_xx.h" header file. I don't know why, and >> haven't >> had time to investigate, but there is a definite improvement when I use >> the >> attached fixed_c55x.h file which has turned all the maths into inline >> functions. > > Did you try with fixed_generic.h or just with fixed_debug.h?

>> Nice call. The culprit is SHRL32. This is not used in many places, and >> in >> most of those, the operand comes from EXTEND32. The only really >> suspicious >> instances is in lsp.c (lsp_interpolate): >> >> spx_word16_t tmp = DIV32_16(SHL32(1 + subframe,14),nb_subframes); >> (subframe is an int) >> ... >> I see that your

It would be great to get some idea of what chips and DSPs people have tried to compile Speex for, and what success they've had. So, if you've tried Speex on a chip, could you take a second to fill in the following and post it to the list? Chip Name: Speex Version: Floating or Fixed: Encode, Decode, Both or Simultaneous: MIPS (if known): Other comments: Many thanks, Gerv

Jean-Marc, >> Build 11169 in SVN works correctly. > > Good. I'll try not to forget the EXTEND32 from now on. > >> I have attached a zip file (renamed >> .txt) with a patch to bits.c to make the byteswapping for TI DSPs >> consistent. > > Seems like unzip can't read it. Either it's in an unknown format or the > file got corrupted. Could simply

Jean-Marc, Here are the patches, broken out one per file. I did some additional work in the testenc files based on Peter Mlakar's post to make it easier (though still a bit klunky) to try different rates. These changes also incorporate the file window.c into the builds, change the decoder startup delay to account for the change in the algorithm delay from 10ms to 5ms, and change bits.c

Jean-Marc, >> >I fixed it in svn. Could you check that? >> >> Now all platforms match again. Note that the measured SNR for this test >> sample is lower than with the broken code (10.87 vs 11.10), but of course >> this is no way to judge the real quality. > > SNR, especially on a single sample, can be very misleading. Yet, could > you just check that the

> The C5x and C6x output diverges in build 10143, which has log message "lpc > floor converted to fixed-point." Also, the measured SNR changed from 11.05 > in builds 9854-10141 to 9.22 and 9.24 in 10143. Actually, build 10143 introduced another bug, that was the reason for the 1.1.11.1 release. > There is just four lines in modes.c which declare the constant, and one

Jean-Marc, >> I incorporated Stuarts fixed_c55x.h file, and that eliminated the >> artifacts, >> at the expense of a ~30% increase in MIPs. Now the male.wav file through >> encoder/decoder produces a bit-exact match with the C64x test that I did >> earlier. I will do some more testing to isolate the, but it may be a few >> days before I get to this task. As

>> You found it. The SHL32 (not SHR32) line fixes the problem. It must be >> doing a 16-bit shift, then extending the result (which is reasonable). >> As >> it happens, that it the same macro which gave us trouble last May >> (25th/26th), when the C55 build was more subtlely broken. > > Yes, that's what I finally remembered. I think I've fixed all

I don't know all the details, but here's a (partial) list of archs on which I've heard of Speex running. I'm sure there are others (especially the float version should really run on any chip with an FPU). float: x86/x86-64 (SSE assembly optimizations provided) PowerPC SPARC fixed: ARM (v4 and v5E) (assembly optimizations provided) Blackfin (assembly optimizations provided) TI

Jim Crichton, I'm trying to run speex on omap 1610 platform and i saw that you have a patch for c55. When i saw your mail about this, i decided to ask you for send me those files above: include\config.h (not automatically generated, sets memory sizes, enables manual alloc) include\speex\speex_config_types.h (match Speex types to compiler types, not generated from types.in