similar to: android tuning

Displaying 20 results from an estimated 3000 matches similar to: "android tuning"

2017 Feb 06
2
[PATCH] Optimize silk_warped_autocorrelation_FIX() for ARM NEON
Hi Jean-Marc, Thanks a lot for reviewing this huge assembly function! silk_warped_autocorrelation_FIX_c()'s kernel part is for( n = 0; n < length; n++ ) { tmp1_QS = silk_LSHIFT32( (opus_int32)input[ n ], QS ); /* Loop over allpass sections */ for( i = 0; i < order; i++ ) { /* Output of allpass section */ tmp2_QS = silk_SMLAWB(
2017 Feb 07
2
[PATCH] Optimize silk_warped_autocorrelation_FIX() for ARM NEON
This is a great idea. But the order (psEncC->shapingLPCOrder) can be configured to 12, 14, 16, 20 and 24 according to complexity parameter. It's hard to get a universal function to handle all these orders efficiently. Any suggestions? Thanks, Linfeng On Mon, Feb 6, 2017 at 12:40 PM, Jean-Marc Valin <jmvalin at jmvalin.ca> wrote: > Hi Linfeng, > > On 06/02/17 02:51 PM,
2017 Feb 07
3
[PATCH] Optimize silk_warped_autocorrelation_FIX() for ARM NEON
Hi Jean-Marc, Thanks for your suggestions. Will get back to you once we have some updates. Linfeng On Mon, Feb 6, 2017 at 5:47 PM, Jean-Marc Valin <jmvalin at jmvalin.ca> wrote: > Hi Linfeng, > > On 06/02/17 07:18 PM, Linfeng Zhang wrote: > > This is a great idea. But the order (psEncC->shapingLPCOrder) can be > > configured to 12, 14, 16, 20 and 24 according to
2017 Apr 05
2
[PATCH] Optimize silk_warped_autocorrelation_FIX() for ARM NEON
I attached a new patch with small cleanup (disassembly is identical as the last patch). We have done the same internal testing as usual. Also, attached 2 failed temporary versions which try to reduce code size (just for code review reference purpose). The new patch of silk_warped_autocorrelation_FIX_neon() has a code size of 3,228 bytes (with gcc). smaller_slower.c has a code size of 2,304
2017 Apr 05
4
[PATCH] Optimize silk_warped_autocorrelation_FIX() for ARM NEON
Thank Jean-Marc! The speedup percentages are all relative to the entire encoder. Comparing to master, this optimization patch speeds up fixed-point SILK encoder on NEON as following: Complexity 5: 6.1% Complexity 6: 5.8% Complexity 8: 5.5% Complexity 10: 4.0% when testing on an Acer Chromebook, ARMv7 Processor rev 3 (v7l), CPU max MHz: 2116.5 Thanks, Linfeng On Wed, Apr 5, 2017 at 11:02 AM,
2006 Mar 15
2
Regarding aov Error()
The following dummy data frame has factor Q (with 2 levels) nesting factor P (with levels p1 and p2 nested under q1, and p3 and p4 nested under q2), but both crossing the random variate s, which has 8 levels. The dependent measure is dv. > # The data frame: > testnest dv s P Q 1 1 s1 p1 q1 2 2 s2 p1 q1 3 1 s3 p1 q1 4 2 s4 p1 q1 5 1 s5 p1 q1 6 3 s6 p1 q1 7 3 s7
2005 May 29
2
"text"-function: adding text in an x,y-plot
Hello R-friends, i have a question to the "text"-function. a little test-dataset for better understanding: -the dataset was imported with read.table(....,header=TRUE) s1-s10 are the samplenames var1 var2 var3 s1 1 1 2 s2 2 3 1 s3 2 2 3 s4 5 4 3 s5 4 2 3 s6 6 3 2 s7 8 5 4 s8 7 2 1 s9 9 3 2
2019 Aug 27
2
TargetRegisterInfo::getCommonSubClass bug, perhaps.
Hi, ABCRegister.td : def SGPR32 : RegisterClass<"ABC", [i32], 16, (add S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 )>; def SFGPR32 : RegisterClass<"ABC", [f32], 16, (add S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 )>; ===== Instruction selection ends: ... t8: i32 = ADDrr t37, t32
2015 Jul 30
0
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
Thanks. This is making a lot more sense now and it's looking like this issue isn't Mips specific. Here's the IR dump before simple register coalescing (note: I've patched the IR printer to print the contents of the regmask): 4480B %vreg260<def> = LDC1 %vreg253, <cp#3>[TF=6]; mem:LD8[ConstantPool] AFGR64:%vreg260 GPR32:%vreg253 4496B %vreg261<def> = FMUL_D32
2009 Dec 05
2
[LLVMdev] use-def chain questions
Hi, all, We are working on a static analysis phase on LLVM's IR, we want to do a backforward phase through the use-def chain, I knew that LLVM had a built-in SSA form which provide the use-def chain for virtual register variables, however, I want to know if you also provide some kinds of use-def chain for memory operations? for example, I have the following source code int foo(int *q, int
2009 Dec 05
0
[LLVMdev] use-def chain questions
On Dec 5, 2009, at 4:02 AM, Tianwei wrote: > Hi, all, > We are working on a static analysis phase on LLVM's IR, we want to do a backforward phase through the use-def chain, I knew that LLVM > had a built-in SSA form which provide the use-def chain for virtual register variables, however, I want to know if you also provide some kinds of use-def chain for memory operations? for
2012 Aug 10
4
subsetting levels of a vector
Hi, I need to subset different levels of vector in a dataset to create a new dataframe that contains only these. These observations are not numerical, so I can't use the subset() function (at least this is the response I get from R). Suppose the dataframe looks like this:   ParticipID    ERP   Electrode 1         s1  0.0370       FP1 2         s2 35.0654       FP2 3         s3
2010 Jan 11
1
HoltWinters Forecasting
Hi R-users, I have a question relating to the HoltWinters() function. I am trying to forecast a series using the Holt Winters methodology but I am getting some unusual results. I had previously been using R for Windows version 2.7.2 and have just started using R 2.9.1. While using version 2.7.2 I was getting reasonable results however upon changing versions I found I started to see unusual
2017 Jan 31
6
[PATCH] Optimize silk_warped_autocorrelation_FIX() for ARM NEON
Hi, Attached is a patch with arm neon optimizations for silk_warped_autocorrelation_FIX(). Please review. Thanks, Felicia -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.xiph.org/pipermail/opus/attachments/20170131/9a912bb4/attachment-0001.html> -------------- next part -------------- A non-text attachment was scrubbed... Name:
2009 Jul 25
1
regex expression to select row or column
I have a multidimensional data which looks like the following: "S1-a" "S2-b" "S3-c" "S4-d" "S5-a" "S6-b" "S7-c" "S8-d" "T1-A" "T1-B" "T1-C" "T1-D" "T2-A" "T2-B" "T2-C" "T2-D" I read it from csv file and would like to have 16
2003 May 22
1
Experimental Design
I don't know if this is the best place to post this question but I will try anyway. I have two experiements for which I use one-way matched-randomized ANOVA for the analysis and I would like to compare different treatments in the two experiments. The only common group in the two experiments are the controls. Is there any ANOVA design that allows me to make this comparison taking into
2011 Sep 21
3
Reading data in lisp format
Hi, I am trying to read the "credit.lisp" file of the Japanese credit database in UCI repository, but it is in lisp format which I do not know how to read. I have not found how to do that in the foreign library http://archive.ics.uci.edu/ml/datasets/Japanese+Credit+Screening <http://archive.ics.uci.edu/ml/datasets/Japanese+Credit+Screening> Could anyone help me? Best
2017 Feb 06
0
[PATCH] Optimize silk_warped_autocorrelation_FIX() for ARM NEON
Hi Linfeng, On 06/02/17 02:51 PM, Linfeng Zhang wrote: > However, the critical thing is that all the states in each stage when > processing input[i] are reused by the next input[i+1]. That is > input[i+1] must wait input[i] for 1 stage, and input[i+2] must wait > input[i+1] for 1 stage, etc. That is indeed the tricky part... and the one I think you could do slightly differently. If
2018 Sep 28
3
error: expected memory with 32-bit signed offset
Hi, I want to encode Loongson ISA initially https://gist.github.com/xiangzhai/8ae6966e2f02a94e180dd16ff1cd60ac gslbx           $2,0($3,$4) It is equivalent to: dadd $1, $3, $4 lb $2,0($1) I just use  mem_simmptr  as the default value of  DAGOperand MO , because  MipsMemAsmOperand  use  parseMemOperand  to parse general  MemOffset  and only *one*  AnyRegister , for example: 0($1) But 
2023 Nov 04
2
EPYC Quantum 1500va
Good Evening, I recently purchased an EPYC quantum UPS. I installed NUT on the home assistant by connecting the UPS via USB and tried all the various drivers in the list, the only one that seems to work is: usbhid-ups with this log: s6-rc: info: service s6rc-oneshot-runner: starting s6-rc: info: service s6rc-oneshot-runner successfully started s6-rc: info: service base-addon-banner: starting