similar to: C 7: smpboot: CPU 16 is now offline

Displaying 20 results from an estimated 1500 matches similar to: "C 7: smpboot: CPU 16 is now offline"

2018 Jun 13
1
C 7: smpboot: CPU 16 is now offline, and slabs...
m.roth at 5-cent.us wrote: > m.roth at 5-cent.us wrote: >> Current kernel, and I just booted, and dmesg shows, of the 32 cores, 0, >> 2, 4 and 6 ok, and *all* other show "is now offline. >> >> What's happening here? <snip> Ok, more info. I found how to online a CPU - echo 1 > /sys/devices/system/cpu/cpu23/online Perhaps I should have started with 1,3,
2018 Jun 13
0
C 7: smpboot: CPU 16 is now offline, and slabs...
m.roth at 5-cent.us wrote: > Current kernel, and I just booted, and dmesg shows, of the 32 cores, 0, 2, > 4 and 6 ok, and *all* other show "is now offline. > > What's happening here? > A followup: I also find a core in /var/spool/abrt, and "reason" is kernel BUG at mm/slub.c:3601! In googling, I see threads about incorrect calculation of slabs. Following one
2007 Feb 23
2
OCFS 1.2.4 memory problems still?
I have a 2 node cluster of HP DL380G4s. These machines are attached via scsi to an external HP disk enclosure. They run 32bit RH AS 4.0 and OCFS 1.2.4, the latest release. They were upgraded from 1.2.3 only a few days after 1.2.4 was released. I had reported on the mailing list that my developers were happy, and things seemed faster. However, twice in that time, the cluster has gone down due
2007 Aug 22
5
Slow concurrent actions on the same LVM logical volume
Hi 2 all ! I have problems with concurrent filesystem actions on a ocfs2 filesystem which is mounted by 2 nodes. OS=RH5ES and OCFS2=1.2.6 F.e.: If I have a LV called testlv which is mounted on /mnt on both servers and I do a "dd if=/dev/zero of=/mnt/test.a bs=1024 count=1000000" on server 1 and do at the same time a du -hs /mnt/test.a it takes about 5 seconds for du -hs to execute: 270M
2020 Sep 07
0
[PATCH v7 67/72] x86/smpboot: Load TSS and getcpu GDT entry before loading IDT
From: Joerg Roedel <jroedel at suse.de> The IDT on 64bit contains vectors which use paranoid_entry() and/or IST stacks. To make these vectors work the TSS and the getcpu GDT entry need to be set up before the IDT is loaded. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/common.c | 23 +++++++++++++++++++++++
2006 May 23
0
RE: [Xen-ia64-devel] Re: PATCH: split smpboot.c and createcpuhotplug.c
>From: Tristan Gingold >Sent: 2006年5月23日 15:30 > >Le Lundi 22 Mai 2006 17:44, Keir Fraser a écrit : >> On 22 May 2006, at 08:57, Tristan Gingold wrote: >> > this patch creates a new file: cpuhotplug.c. The content is the >xenbus >> > handler part of smpboot.c. The purpose is to be able to share this >> > part with >> > other architectures.
2008 Aug 22
3
sun4v arch
I would also like to help as well. As KMacy knows before i asked a lot of questions for T2 types of servers but unfortunately i have no more access to those kind of hardware as well. I;m willing to participate if a team will be formated.
2020 Sep 08
1
[PATCH v7 67/72] x86/smpboot: Load TSS and getcpu GDT entry before loading IDT
On Mon, Sep 07, 2020 at 03:16:08PM +0200, Joerg Roedel wrote: > From: Joerg Roedel <jroedel at suse.de> > > The IDT on 64bit contains vectors which use paranoid_entry() and/or IST > stacks. To make these vectors work the TSS and the getcpu GDT entry need > to be set up before the IDT is loaded. > > Signed-off-by: Joerg Roedel <jroedel at suse.de> > --- >
2012 Jun 01
0
[PATCH 06/27] xen, smpboot: Use generic SMP booting infrastructure
Convert xen to use the generic framework to boot secondary CPUs. Cc: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com> Cc: Jeremy Fitzhardinge <jeremy at goop.org> Cc: Thomas Gleixner <tglx at linutronix.de> Cc: Ingo Molnar <mingo at redhat.com> Cc: "H. Peter Anvin" <hpa at zytor.com> Cc: x86 at kernel.org Cc: xen-devel at lists.xensource.com Cc:
2012 Jun 01
0
[PATCH 06/27] xen, smpboot: Use generic SMP booting infrastructure
Convert xen to use the generic framework to boot secondary CPUs. Cc: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com> Cc: Jeremy Fitzhardinge <jeremy at goop.org> Cc: Thomas Gleixner <tglx at linutronix.de> Cc: Ingo Molnar <mingo at redhat.com> Cc: "H. Peter Anvin" <hpa at zytor.com> Cc: x86 at kernel.org Cc: xen-devel at lists.xensource.com Cc:
2020 Aug 24
0
[PATCH v6 70/76] x86/smpboot: Setup TSS for starting AP
From: Joerg Roedel <jroedel at suse.de> Set up the TSS for starting APs before they are kicked. This allows the APs to use IST in early exception handling. Also load the TSS early if the TSS entry in the GDT is present. This makes sure a TSS is only loaded when it has been set up. Signed-off-by: Joerg Roedel <jroedel at suse.de> Link:
2014 Aug 01
2
[RFC PATCH 00/11] Refactor MSI to support Non-PCI device
On Wednesday 30 July 2014, Yijing Wang wrote: > >>> > >>> The other part I'm not completely sure about is how you want to > >>> have MSIs map into normal IRQ descriptors. At the moment, all > >>> MSI users are based on IRQ numbers, but this has known scalability problems. > >> > >> Hmmm, I still use the IRQ number to map the
2014 Aug 01
2
[RFC PATCH 00/11] Refactor MSI to support Non-PCI device
On Wednesday 30 July 2014, Yijing Wang wrote: > >>> > >>> The other part I'm not completely sure about is how you want to > >>> have MSIs map into normal IRQ descriptors. At the moment, all > >>> MSI users are based on IRQ numbers, but this has known scalability problems. > >> > >> Hmmm, I still use the IRQ number to map the
2007 Feb 19
10
"dst cache overflow" messages and crash
Hi, I regularly have errors (kernel: dst cache overflow) and crash of a firewall under Linux 2.6.17 and the route patch from Julian Anastasov. With rtstat I see that the route cache size increases regularly without never decreasing. I have this parameters: fw:/proc/sys/net/ipv4/route# grep . * error_burst:1250 error_cost:250 gc_elasticity:15 gc_interval:60 gc_min_interval:0
2014 Aug 04
1
[RFC PATCH 00/11] Refactor MSI to support Non-PCI device
On Monday 04 August 2014, Yijing Wang wrote: > I have another question is some drivers will request more than one > MSI/MSI-X IRQ, and the driver will use them to process different things. > Eg. network driver generally uses one of them to process trivial network thins, > and others to transmit/receive data. > > So, in this case, it seems to driver need to touch the IRQ numbers.
2014 Aug 04
1
[RFC PATCH 00/11] Refactor MSI to support Non-PCI device
On Monday 04 August 2014, Yijing Wang wrote: > I have another question is some drivers will request more than one > MSI/MSI-X IRQ, and the driver will use them to process different things. > Eg. network driver generally uses one of them to process trivial network thins, > and others to transmit/receive data. > > So, in this case, it seems to driver need to touch the IRQ numbers.
2017 Dec 19
5
[Bug 104340] New: Memory leak with GEM objects
https://bugs.freedesktop.org/show_bug.cgi?id=104340 Bug ID: 104340 Summary: Memory leak with GEM objects Product: xorg Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouveau at
2008 Apr 02
2
Memory use and a few other things
Hello, First of all thanks a lot for working on this free nvidia driver. 1.) I am using Fedora9-Beta, and on my NV17/64mb (or NV18?) powered Laptop the nouveau driver uses about 300mb RAM. Is there any way I can decrease that? 2.) Font rendering is very slow. running "x11perf --aa10text" I only get 40k glyphs/s. Is there any way I can improve text performance? 3.) I would like to
2012 Nov 15
3
Likely mem leak in 3.7
Starting with 3.7 rc1, my workstation seems to loose ram. Up until (and including) 3.6, used-(buffers+cached) was roughly the same as sum(rss) (taking shared into account). Now there is an approx 6G gap. When the box first starts, it is clearly less swappy than with <= 3.6; I can''t tell whether that is related. The reduced swappiness persists. It seems to get worse when I update
2010 Aug 19
3
SSD caching of MDT
Article by Jeff Layton: http://www.linux-mag.com/id/7839 anyone have views on whether this sort of caching would be useful for the MDT? My feeling is that MDT reads are probably pretty random but writes might benefit...? GREG -- Greg Matthews 01235 778658 Senior Computer Systems Administrator Diamond Light Source, Oxfordshire, UK