similar to: how does setMemory work?

Assume an architecture that has multiple condition code registers, e.g., powerpc. Now assume that there are predicate instructions like thumb2, but can specify which condition code register they refer to. Now also assume that these predicate instructions themselves are predicatible, if executed they change the current predication state. Can LLVM handle multiple levels of predication? When is

Hello. I'm trying to understand how fastcall works. As far as I know, first two integer type arguments are passed in ecx and edx. I tested several test, but the result was different from what I expected #1 typedef struct _data_t { int d; } data_t; void __attribute__((fastcall)) test_suuu(data_t s, unsigned int a, unsigned int b, unsigned int c); unsigned int a is passed

I have a global 2-D array ARRAY[N][M] and I am accessing it inside the for loop like this: for (i...) for (j ...) ARRAY[i][j] ... So nothing really weird is happening. If I look at the generated IR, it is also fairly straight forward. @ARRAY0 = dso_local global [32 x [32 x i32]] zeroinitializer, section ".slow_mem", align 32, !dbg !84 ... %45 = getelementptr inbounds [32 x [32 x

Hi All, I have got one domination error after running LoopVectorizer with VPlanNatviePath. Let's see simple IR snippet after loop vectorization with VPlanNatviePath. vector.body: ... br label %for.body10.preheader67 for.body10.preheader67: ; preds = %for.cond.cleanup972, %vector.body %vec.phi = phi <4 x i64> [ zeroinitializer, %for.cond.cleanup972 ], [ %8,

I want to know all the optimization applied by the passes. I found two options in clang 1. -fsave-optimization-record 2. -Rpass-analysis=... However, they have nothing to do with the interaction btw IR files(.ll) Is there any tool that records all optimizations on IR file? -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi everyone. : ) I meet problem when use form tag in actionmailer. (content-type is text/html, surely) I want to use form action in actionmailer''s view (.rhtml) for some reason. 1. I use start_form_tag helper method as normally, but how I can ? I did <%= start_form_tag :action => "http://myhostname/mycontroller/myaction" %> or <%= start_form_tag :action =>

Hi,  I''m currently stuck with creating VM which cannot boot with disk using blktap2 driver. I''ve been searching nearly a whole week and I couldn''t get a answer. When creating vm with blktap2, it keep shows a error:   libxl: debug: libxl_device.c:200:disk_try_backend: Disk vdev=xvda, backend tap unsuitable because blktap not available.  VM configuration (XML):

> for example: > 1. Turn C/C++ language into C_llvmIR assembly language using Clang > 2. Turn Fortran language into Fortran_llvmIR assembly language using > Dragonegg > 3. Turn Python language into Python_llvmIR assembly language using > Unladen-Swallow > 4. Connect each llvm IR > > Is this possible? I guess you want to link LLVM IR generated for different language

I want to connect each llvm ir for example: 1. Turn C/C++ language into C_llvmIR assembly language using Clang 2. Turn Fortran language into Fortran_llvmIR assembly language using Dragonegg 3. Turn Python language into Python_llvmIR assembly language using Unladen-Swallow 4. Connect each llvm IR Is this possible? Wonjun, Choi -------------- next part -------------- An HTML attachment was

my system configuration xen 3.4.2, oprofile 0.9.5( xenoprof patched ), dom0( jeremy''s pvops kernel 2.6.31.6 - patched dullor''s xenoprof patch ), domU( vanilla kernel 2.6.32 with paravirt enabled ), distribution( ubuntu 9.10 ) In passive mode, xenoprof seems to work well, opreport showed good information. but, in active mode, it seems not to be done correctly. my command is

Hi all, I have faced a little bit of a strange transformation from the TailDuplicatePass In CodeGen. When the pass clones the contents of TailBB into PredBB, the bundled instructions in TailBB are not bundled in PredBB. I think the reason why it is not bundled is that the 'DuplicateInstruction' function does not set up the flag of the first instruction of the bundle in PredBB when it

Hi all, I want to attach cdrom by libvirt.py .But can't find a func in libvirt.py can finish this work. Who can help me ? Regard -- Seven Ling E-mail: jiejie.ling at qq.com

2014년 2월 11일 오후 10:00에 Eric Blake <eblake@redhat.com> 작성: On 02/11/2014 12:20 AM, Kim Larry wrote: libvirtd version is 1.1.4 and using Xen for hypervisor. I'm not as familiar with the xen hypervisor as with qemu; it may just be the case that no one has coded the xen driver to send a shutdown event. At any rate, I can confirm that with the qemu driver, shutdown events are delivered. It

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello everyone, Is this being worked on? I rather need this thing... Although my system is Debian Lenny, not RH: kulfon 10.0.0.228 /etc/default % dpkg -l | grep libvirt ii libvirt-bin 0.4.6-10+lenny1 the programs for the libvirt library ii libvirt0 0.4.6-10+lenny1 library for

Hi guys, When a guest's memory is dynamically reduced with setMemory API (and "balloon" QMP API), I'm wondering whether the virtio-balloon driver in the guest is consuming such reduced memory. If so, how can I see that the memory virtio-balloon is consuming? and is it possible the virtio-balloon has such a huge memory even though it's a kernel module?? Thanks,

I''m in the midst of a few new Rails deployments as well as being tasked to revise an existing older deployment to help improve performance. So, I''m wondering what sort of setup is preferable these days for a dedicated server? The basics I''m aiming to start with are the latest CentOS/RHEL, PostgreSQL, Ruby 2.x, Rails and Apache. Is Passenger still the way to go these

Hi JinGu, We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved. Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them.

On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote: > Hi Andy, > > I am trying to schedule and packetize instructions for VLIW at post-RA > stage or final codegen stage, where code transformations are not allowed > any more, because hardware can not resolve resource conflict. There is a > simple example as following: > > ADD dest_reg1, src_reg1,

I want to call C function from fortran or call fortran function from C. 2011년 6월 15일 오전 11:59, 陳韋任 <chenwj at iis.sinica.edu.tw>님의 말: > > for example: > > 1. Turn C/C++ language into C_llvmIR assembly language using Clang > > 2. Turn Fortran language into Fortran_llvmIR assembly language using > > Dragonegg > > 3. Turn Python language into Python_llvmIR

You are right. Thanks! I fixed that one as well as some other issues. I built LLVM-8 with Debug + no-rtti. But it now has the following error: Stack dump: 0. Program arguments: clang-8 -cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -disable-free -main-file-name time-1.7.c -mrelocation-model static -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases