Displaying 20 results from an estimated 10000 matches similar to: "[PATCH RFC v1 04/18] iommu/hyperv: don't setup IRQ remapping when running as root"
2020 Jun 11
2
AMD IOMMU + SME + amdgpu regression
Hi,
amdgpu + IOMMU + SME is now working for me on 5.7, yay! But, it is
broken on torvalds master, boo. On boot, depending on which exact commit
I test, it either hangs immediately (with built-in driver, before
starting initramfs), displays some errors then hangs, or spams the
screen with many amdgpu errors.
I bisected the black screen hang to:
commit dce8d6964ebdb333383bacf5e7ab8c27df151218
2020 Jun 11
2
AMD IOMMU + SME + amdgpu regression
Hi,
amdgpu + IOMMU + SME is now working for me on 5.7, yay! But, it is
broken on torvalds master, boo. On boot, depending on which exact commit
I test, it either hangs immediately (with built-in driver, before
starting initramfs), displays some errors then hangs, or spams the
screen with many amdgpu errors.
I bisected the black screen hang to:
commit dce8d6964ebdb333383bacf5e7ab8c27df151218
2020 Apr 14
0
[PATCH v2 23/33] iommu/mediatek-v1 Convert to probe/release_device() call-backs
From: Joerg Roedel <jroedel at suse.de>
Convert the Mediatek-v1 IOMMU driver to use the probe_device() and
release_device() call-backs of iommu_ops, so that the iommu core code
does the group and sysfs setup.
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
drivers/iommu/mtk_iommu_v1.c | 50 +++++++++++++++---------------------
1 file changed, 20 insertions(+), 30 deletions(-)
2020 Feb 11
2
[PATCH 14/62] x86/boot/compressed/64: Add stage1 #VC handler
On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Joerg Roedel <jroedel at suse.de>
>
> Add the first handler for #VC exceptions. At stage 1 there is no GHCB
> yet becaue we might still be on the EFI page table and thus can't map
> memory unencrypted.
>
> The stage 1 handler is limited to the MSR based protocol to talk to
2020 Feb 11
2
[PATCH 14/62] x86/boot/compressed/64: Add stage1 #VC handler
On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Joerg Roedel <jroedel at suse.de>
>
> Add the first handler for #VC exceptions. At stage 1 there is no GHCB
> yet becaue we might still be on the EFI page table and thus can't map
> memory unencrypted.
>
> The stage 1 handler is limited to the MSR based protocol to talk to
2020 May 19
2
[PATCH v3 35/75] x86/head/64: Build k/head64.c with -fno-stack-protector
On Tue, Apr 28, 2020 at 11:28 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Joerg Roedel <jroedel at suse.de>
>
> The code inserted by the stack protector does not work in the early
> boot environment because it uses the GS segment, at least with memory
> encryption enabled. Make sure the early code is compiled without this
> feature enabled.
>
>
2020 May 19
2
[PATCH v3 35/75] x86/head/64: Build k/head64.c with -fno-stack-protector
On Tue, Apr 28, 2020 at 11:28 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Joerg Roedel <jroedel at suse.de>
>
> The code inserted by the stack protector does not work in the early
> boot environment because it uses the GS segment, at least with memory
> encryption enabled. Make sure the early code is compiled without this
> feature enabled.
>
>
2020 Feb 11
1
[PATCH 19/62] x86/sev-es: Add support for handling IOIO exceptions
On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Tom Lendacky <thomas.lendacky at amd.com>
>
> Add support for decoding and handling #VC exceptions for IOIO events.
>
> Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
> [ jroedel at suse.de: Adapted code to #VC handling framework ]
> Co-developed-by: Joerg Roedel
2020 Feb 11
2
[PATCH 23/62] x86/idt: Move IDT to data segment
On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Joerg Roedel <jroedel at suse.de>
>
> With SEV-ES, exception handling is needed very early, even before the
> kernel has cleared the bss segment. In order to prevent clearing the
> currently used IDT, move the IDT to the data segment.
Ugh. At the very least this needs a comment in the
2020 Feb 11
2
[PATCH 23/62] x86/idt: Move IDT to data segment
On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Joerg Roedel <jroedel at suse.de>
>
> With SEV-ES, exception handling is needed very early, even before the
> kernel has cleared the bss segment. In order to prevent clearing the
> currently used IDT, move the IDT to the data segment.
Ugh. At the very least this needs a comment in the
2020 Feb 12
2
[PATCH 23/62] x86/idt: Move IDT to data segment
> On Feb 12, 2020, at 3:55 AM, Joerg Roedel <joro at 8bytes.org> wrote:
>
> ?On Tue, Feb 11, 2020 at 02:41:25PM -0800, Andy Lutomirski wrote:
>>> On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>>>
>>> From: Joerg Roedel <jroedel at suse.de>
>>>
>>> With SEV-ES, exception handling is needed very
2020 Feb 12
2
[PATCH 23/62] x86/idt: Move IDT to data segment
> On Feb 12, 2020, at 3:55 AM, Joerg Roedel <joro at 8bytes.org> wrote:
>
> ?On Tue, Feb 11, 2020 at 02:41:25PM -0800, Andy Lutomirski wrote:
>>> On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>>>
>>> From: Joerg Roedel <jroedel at suse.de>
>>>
>>> With SEV-ES, exception handling is needed very
2020 Aug 29
2
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
On Mon, Aug 24, 2020 at 10:54:33AM +0200, Joerg Roedel wrote:
> From: Joerg Roedel <jroedel at suse.de>
>
> Early exception handling will use rd/wrgsbase in paranoid_entry/exit.
> Enable the feature to avoid #UD exceptions on boot APs.
>
> Signed-off-by: Joerg Roedel <jroedel at suse.de>
> Link: https://lore.kernel.org/r/20200724160336.5435-38-joro at 8bytes.org
2020 Feb 11
1
[PATCH 25/62] x86/head/64: Install boot GDT
On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Joerg Roedel <jroedel at suse.de>
>
> Handling exceptions during boot requires a working GDT. The kernel GDT
> is not yet ready for use, so install a temporary boot GDT.
>
> Signed-off-by: Joerg Roedel <jroedel at suse.de>
> ---
> arch/x86/kernel/head_64.S | 26
2020 Aug 29
2
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
On Mon, Aug 24, 2020 at 10:54:33AM +0200, Joerg Roedel wrote:
> From: Joerg Roedel <jroedel at suse.de>
>
> Early exception handling will use rd/wrgsbase in paranoid_entry/exit.
> Enable the feature to avoid #UD exceptions on boot APs.
>
> Signed-off-by: Joerg Roedel <jroedel at suse.de>
> Link: https://lore.kernel.org/r/20200724160336.5435-38-joro at 8bytes.org
2020 Feb 11
1
[PATCH 18/62] x86/boot/compressed/64: Setup GHCB Based VC Exception handler
On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote:
>
> From: Joerg Roedel <jroedel at suse.de>
>
> Install an exception handler for #VC exception that uses a GHCB. Also
> add the infrastructure for handling different exit-codes by decoding
> the instruction that caused the exception and error handling.
>
> diff --git
2020 Apr 14
0
[PATCH v2 04/33] iommu/vt-d: Wire up iommu_ops->def_domain_type
From: Joerg Roedel <jroedel at suse.de>
The Intel VT-d driver already has a matching function to determine the
default domain type for a device. Wire it up in intel_iommu_ops.
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
drivers/iommu/intel-iommu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index
2020 Apr 14
0
[PATCH v2 18/33] iommu/pamu: Convert to probe/release_device() call-backs
From: Joerg Roedel <jroedel at suse.de>
Convert the PAMU IOMMU driver to use the probe_device() and
release_device() call-backs of iommu_ops, so that the iommu core code
does the group and sysfs setup.
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
drivers/iommu/fsl_pamu_domain.c | 22 +++++-----------------
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git
2020 Sep 15
0
[PATCH RFC v1 07/18] x86/hyperv: extract partition ID from Microsoft Hypervisor if necessary
Wei Liu <wei.liu at kernel.org> writes:
> We will need the partition ID for executing some hypercalls later.
>
> Signed-off-by: Lillian Grassin-Drake <ligrassi at microsoft.com>
> Co-Developed-by: Sunil Muthuswamy <sunilmut at microsoft.com>
> Signed-off-by: Wei Liu <wei.liu at kernel.org>
> ---
> arch/x86/hyperv/hv_init.c | 26
2020 Aug 28
0
[PATCH v6 27/76] x86/sev-es: Add CPUID handling to #VC handler
On Thu, Aug 27, 2020 at 06:48:10PM -0400, Arvind Sankar wrote:
> On Mon, Aug 24, 2020 at 10:54:22AM +0200, Joerg Roedel wrote:
> > From: Tom Lendacky <thomas.lendacky at amd.com>
> >
> > Handle #VC exceptions caused by CPUID instructions. These happen in
> > early boot code when the KASLR code checks for RDTSC.
> >
> > Signed-off-by: Tom Lendacky