similar to: [PATCH 0/7] Hyper-V Synthetic interrupt controller

On 10/09/2015 07:39 AM, Denis V. Lunev wrote: > From: Andrey Smetanin <asmetanin at virtuozzo.com> > > A new vcpu exit is introduced to notify the userspace of the > changes in Hyper-V synic configuraion triggered by guest writing to the s/configuraion/configuration/ Is 'synic' intended? Is it short for something (if so, spelling it out may help)? > +++

On 10/09/2015 07:39 AM, Denis V. Lunev wrote: > From: Andrey Smetanin <asmetanin at virtuozzo.com> > > A new vcpu exit is introduced to notify the userspace of the > changes in Hyper-V synic configuraion triggered by guest writing to the s/configuraion/configuration/ Is 'synic' intended? Is it short for something (if so, spelling it out may help)? > +++

This patchset implements the KVM part of the synthetic interrupt controller (SynIC) which is a building block of the Hyper-V paravirtualized device bus (vmbus). SynIC is a lapic extension, which is controlled via MSRs and maintains for each vCPU - 16 synthetic interrupt "lines" (SINT's); each can be configured to trigger a specific interrupt vector optionally with auto-EOI

This patchset implements the KVM part of the synthetic interrupt controller (SynIC) which is a building block of the Hyper-V paravirtualized device bus (vmbus). SynIC is a lapic extension, which is controlled via MSRs and maintains for each vCPU - 16 synthetic interrupt "lines" (SINT's); each can be configured to trigger a specific interrupt vector optionally with auto-EOI

This patchset implements the KVM part of the synthetic interrupt controller (synic) which is a building block of the Hyper-V paravirtualized device bus (vmbus). Synic is a lapic extension, which is controlled via MSRs and maintains for each vCPU - 16 synthetic interrupt "lines" (SINT's); each can be configured to trigger a specific interrupt vector optionally with auto-EOI

This patchset implements the KVM part of the synthetic interrupt controller (synic) which is a building block of the Hyper-V paravirtualized device bus (vmbus). Synic is a lapic extension, which is controlled via MSRs and maintains for each vCPU - 16 synthetic interrupt "lines" (SINT's); each can be configured to trigger a specific interrupt vector optionally with auto-EOI

Hyper-V SynIC is a Hyper-V synthetic interrupt controller. The test runs on every vCPU and performs the following steps: * read from all Hyper-V SynIC MSR's * setup Hyper-V SynIC evt/msg pages * setup SINT's routing * inject SINT's into destination vCPU by 'hyperv-synic-test-device' * wait for SINT's isr's completion * clear Hyper-V SynIC evt/msg pages and destroy

Hyper-V SynIC is a Hyper-V synthetic interrupt controller. The test runs on every vCPU and performs the following steps: * read from all Hyper-V SynIC MSR's * setup Hyper-V SynIC evt/msg pages * setup SINT's routing * inject SINT's into destination vCPU by 'hyperv-synic-test-device' * wait for SINT's isr's completion * clear Hyper-V SynIC evt/msg pages and destroy

Signed-off-by: Andrey Smetanin <asmetanin at virtuozzo.com> Reviewed-by: Roman Kagan <rkagan at virtuozzo.com> Signed-off-by: Denis V. Lunev <den at openvz.org> CC: Vitaly Kuznetsov <vkuznets at redhat.com> CC: "K. Y. Srinivasan" <kys at microsoft.com> CC: Gleb Natapov <gleb at kernel.org> CC: Paolo Bonzini <pbonzini at redhat.com> CC: Roman

On 09/10/2015 15:39, Denis V. Lunev wrote: > From: Andrey Smetanin <asmetanin at virtuozzo.com> > > A new vcpu exit is introduced to notify the userspace of the > changes in Hyper-V synic configuraion triggered by guest writing to the > corresponding MSRs. > > Signed-off-by: Andrey Smetanin <asmetanin at virtuozzo.com> > Reviewed-by: Roman Kagan <rkagan at

On 09/10/2015 15:39, Denis V. Lunev wrote: > From: Andrey Smetanin <asmetanin at virtuozzo.com> > > A new vcpu exit is introduced to notify the userspace of the > changes in Hyper-V synic configuraion triggered by guest writing to the > corresponding MSRs. > > Signed-off-by: Andrey Smetanin <asmetanin at virtuozzo.com> > Reviewed-by: Roman Kagan <rkagan at

From: Andrey Smetanin <asmetanin at virtuozzo.com> Hypervisor Top Level Functional Specification v3.1/4.0 notes that cpuid (0x40000003) EDX's 10th bit should be used to check that Hyper-V guest crash MSR's functionality available. This patch should fix this recognition. Currently the code checks EAX register instead of EDX. Signed-off-by: Andrey Smetanin <asmetanin at

From: Andrey Smetanin <asmetanin at virtuozzo.com> Hypervisor Top Level Functional Specification v3.1/4.0 notes that cpuid (0x40000003) EDX's 10th bit should be used to check that Hyper-V guest crash MSR's functionality available. This patch should fix this recognition. Currently the code checks EAX register instead of EDX. Signed-off-by: Andrey Smetanin <asmetanin at

On 11/02/2015 03:16 PM, Paolo Bonzini wrote: > On 26/10/2015 10:56, Andrey Smetanin wrote: >> Hyper-V SynIC is a Hyper-V synthetic interrupt controller. >> >> The test runs on every vCPU and performs the following steps: >> * read from all Hyper-V SynIC MSR's >> * setup Hyper-V SynIC evt/msg pages >> * setup SINT's routing >> * inject SINT's

On 11/02/2015 03:16 PM, Paolo Bonzini wrote: > On 26/10/2015 10:56, Andrey Smetanin wrote: >> Hyper-V SynIC is a Hyper-V synthetic interrupt controller. >> >> The test runs on every vCPU and performs the following steps: >> * read from all Hyper-V SynIC MSR's >> * setup Hyper-V SynIC evt/msg pages >> * setup SINT's routing >> * inject SINT's

--- celt/cpu_support.h | 3 ++- celt/x86/x86cpu.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/celt/cpu_support.h b/celt/cpu_support.h index 133abbf..68fc606 100644 --- a/celt/cpu_support.h +++ b/celt/cpu_support.h @@ -45,7 +45,8 @@ #elif (defined(OPUS_X86_MAY_HAVE_SSE) && !defined(OPUS_X86_PRESUME_SSE)) || \ (defined(OPUS_X86_MAY_HAVE_SSE2) &&

The attached patch cleans up Opus's x86 intrinsics configury. It: * Makes ?enable-intrinsics work with clang and other non-GCC compilers * Enables RTCD for the floating-point-mode SSE code in Celt. * Disables use of RTCD in cases where the compiler targets an instruction set by default. * Enables the SSE4.1 Silk optimizations that apply to the common parts of Silk when Opus is built in

From: Andrey Smetanin <asmetanin at virtuozzo.com> A new vcpu exit is introduced to notify the userspace of the changes in Hyper-V synic configuraion triggered by guest writing to the corresponding MSRs. Signed-off-by: Andrey Smetanin <asmetanin at virtuozzo.com> Reviewed-by: Roman Kagan <rkagan at virtiozzo.com> Signed-off-by: Denis V. Lunev <den at openvz.org> CC:

From: Andrey Smetanin <asmetanin at virtuozzo.com> A new vcpu exit is introduced to notify the userspace of the changes in Hyper-V SynIC configuration triggered by guest writing to the corresponding MSRs. Signed-off-by: Andrey Smetanin <asmetanin at virtuozzo.com> Reviewed-by: Roman Kagan <rkagan at virtiozzo.com> Signed-off-by: Denis V. Lunev <den at openvz.org> CC:

Hello, guys! How's it going? I would like to offer you myself again to implement one of the ideas during the GSoC 2012. I want to take care of the "Learning To Rank" project, but I would also be glad to pick the "QueryParser reimplementation", "Dynamic Snippets", "Gmane Search improvements" or even "Replace socket code with ZeroMQ" project (I