similar to: [klibc:master] mips/mips64: simplify crt0 code

Commit-ID: 3438d861da2e6939a6b0d454ffe247c19ead5993 Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=3438d861da2e6939a6b0d454ffe247c19ead5993 Author: Dejan Latinovic <Dejan.Latinovic at imgtec.com> AuthorDate: Thu, 5 Mar 2015 16:51:45 -0800 Committer: H. Peter Anvin <hpa at linux.intel.com> CommitDate: Thu, 5 Mar 2015 16:51:45 -0800

Hi, I noticed that klibc started crashing on 64-bit MIPS and in my quest to fix the bug I got a bit carried away and fixed a few other things as well. Here are various miscellaneous MIPS patches, although the first patch is the important one. Thanks, James *** BLURB HERE *** James Cowgill (5): mips64: compile with -mno-abicalls mips: use -Ttext-segment when linking shared library

Commit-ID: 0a14ced5d7d0c23ece5d2828cbdff6cb1c589b8d Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=0a14ced5d7d0c23ece5d2828cbdff6cb1c589b8d Author: James Cowgill <james.cowgill at mips.com> AuthorDate: Fri, 2 Mar 2018 14:48:21 +0000 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 03:08:04 +0000 [klibc] mips64: compile with

Commit-ID: 8b15382a33823d38599347e90022abfcdc70fc68 Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=8b15382a33823d38599347e90022abfcdc70fc68 Author: James Cowgill <james.cowgill at mips.com> AuthorDate: Fri, 2 Mar 2018 08:36:45 -0800 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 03:08:04 +0000 [klibc] mips64: remove __unused

Actually, GCC will generate non-PIC for n64. Maybe that is a recent addition, but we are using its results. Even if PIC may be faster and smaller code, it seems that non-PIC is still useful for bare-metal. That's the driver of my interest. I guess we can just test what happens when that part of the conditional is removed. As a side note, if it isn't supported then we should probably

Commit-ID: 048bfb0df170d4a43142adcee8a2dffdfc2c1e9f Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=048bfb0df170d4a43142adcee8a2dffdfc2c1e9f Author: James Cowgill <james.cowgill at mips.com> AuthorDate: Fri, 2 Mar 2018 08:33:01 -0800 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 03:08:04 +0000 [klibc] mips: use -Ttext-segment

From: Dejan Latinovic <Dejan.Latinovic at imgtec.com> --- usr/include/arch/mips64/klibc/archconfig.h | 3 + usr/include/arch/mips64/klibc/archsetjmp.h | 39 ++++++ usr/include/arch/mips64/machine/asm.h | 76 ++++++++++ usr/include/fcntl.h | 2 +- usr/include/sys/md.h | 1 + usr/include/sys/resource.h | 4 +-

Hi LLVM developers, GCC[1] is able to use Loongson ISA[2] for instruction selection: $ cat hello.c #include <stdio.h> int main(int argc, char *argv[]) { printf("Hello World\n"); return 0; } $ gcc -O0 -S hello.c $ cat hello.s .file 1 "hello.c" .section .mdebug.abi64 .previous .nan legacy .gnu_attribute 4, 1 .abicalls

- my old email address. The ISA_* classes might not be the best choice for this. There's an overall hierarchy and ordering to the ISA_* classes since they represent the generations of the MIPS ISA. If these extensions are available in Loongson chips based on MIPS32r1 and MIPS32r2 for example, it becomes difficult to describe with ISA_* classes without duplicating instruction definitions or

Commit-ID: edf92a18d1f1725896c928cbcf580abc268f307c Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=edf92a18d1f1725896c928cbcf580abc268f307c Author: James Cowgill <james.cowgill at mips.com> AuthorDate: Fri, 2 Mar 2018 08:33:03 -0800 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 03:08:04 +0000 [klibc] mips: don't save

The latest TOT of libunwind fails for me when I build UnwindRegistersSave.S for the Mips. My copy of clang uses a 2.25 binutils Mips assembler. This is the message I get: "/home/rich/ellcc/bin/mips-elf-as" -o /tmp/UnwindRegistersSave-a2c974.o -EL /tmp/UnwindRegistersSave-545450.s src/UnwindRegistersSave.S: Assembler messages: src/UnwindRegistersSave.S:99: Error: opcode not

Has anyone experimented with generating non-PIC for MIPS64 and the n64 ABI? Currently MipsISelLowering.cpp uses conditions like: if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { } around any PIC code generation. Is generating non-PIC just untested, or is it known not to work? I can't find any discussion of it anywhere. I ran into this when trying to see why

This patch is needed to allow klibc to be compiled on a mips compiler configured to use the FPXX ABI (which is in GCC 5). In that ABI the odd numbered FPU registers cannot be used directly, but they can be accessed using the double word sdc1 and ldc1 instructions. See this page for more info: https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking Signed-off-by: James Cowgill

On Wed, Sep 16, 2015 at 01:50:08PM +0530, Sudip Mukherjee wrote: > Hi, > While crosscompiling the kernel for openrisc with allmodconfig the build > failed with the error: > drivers/vhost/vhost.c: In function 'vhost_vring_ioctl': > drivers/vhost/vhost.c:818:3: error: call to '__compiletime_assert_818' declared with attribute error: BUILD_BUG_ON failed: __alignof__

The parts of klibc specific to the mips architecture. Signed-off-by: H. Peter Anvin <hpa at zytor.com> --- commit 8dc79563c06020d8844b9e9b821741828039b59e tree b957c8fb1fddf486f5c26b1880726051d4f6aaad parent bc9b363b31d301ab94c115cccc2e079c0d318498 author H. Peter Anvin <hpa at zytor.com> Sun, 25 Jun 2006 16:58:31 -0700 committer H. Peter Anvin <hpa at zytor.com> Sun, 25 Jun

Instruction selection happens on a different IR: SelectionDAG. In this IR, there are sign-extending loads that the IR converter will use, and are used for example to load 8/16-bit values into 32-bit registers (with sign or zero extension). Any optimizations performed during codegen will be in this representation, or even MachineInstr form, which is post-isel and any sign-extension information

Hi all, when compiling code like short ptr * = some_address; int val; val = *ptr; if (val>2047) val = 2047; else if (val<-2048) val = -2048. // other things done that require val to be an int ... The load operation is represented by a load and a sign extension operation in the LLVM IR. On most target architectures, there exist signed halfword load instructions, so the load and

Introduce Cortex-A7 with a scalable proc_info_list which including cpu id and cpu initialize function. In head.S, search cpu specific MIDR in procinfo and call such initialize function. Currently, support Cortex-A7 and Cortex-A15. Signed-off-by: Bamvor Jian Zhang <bjzhang@suse.com> --- changes since v2 1), define cpu_init function instead of assemble jump code in struct proc_info_list 2),

On Mon, Jan 21, 2013 at 9:16 AM, Bjorn De Sutter < bjorn.desutter at elis.ugent.be> wrote: > On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> > wrote: > > Instruction selection happens on a different IR: SelectionDAG. In this > IR, there are sign-extending loads that the IR converter will use, and are > used for example to load 8/16-bit

On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> wrote: > Instruction selection happens on a different IR: SelectionDAG. In this IR, there are sign-extending loads that the IR converter will use, and are used for example to load 8/16-bit values into 32-bit registers (with sign or zero extension). Any optimizations performed during codegen will be in this