similar to: [PATCH] drm/nouveau: remove redundant check

Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- drivers/gpu/drm/nouveau/nv04_crtc.c | 37 +++++++++++++++++++++------------- 1 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c index 2ab9f30..0a5cfc1 100644 --- a/drivers/gpu/drm/nouveau/nv04_crtc.c +++ b/drivers/gpu/drm/nouveau/nv04_crtc.c

Hello Ben Skeggs, The patch 88524bc06926: "drm/nouveau/devinit: move simple pll setting routines to devinit" from Mar 5, 2013, leads to the following static checker warning: drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c:53 nv50_devinit_pll_set() info: return a literal instead of 'ret' drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 34 int 35

This should probably be folded into the previous patch to avoid breaking bisectability on nve0 On Thu, Sep 4, 2014 at 10:58 AM, Roy Spliet <rspliet at eclipso.eu> wrote: > This used to be done implicitly > > Signed-off-by: Roy Spliet <rspliet at eclipso.eu> > --- > drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | 5 +++++ > 1 file changed, 5 insertions(+) >

Hi guys! I'm getting the following warn on 4.15-rc1, on GTX 560 Ti: [ 9.430433] nouveau 0000:01:00.0: NVIDIA GF114 (0ce000a1) ... [ 9.585172] nouveau 0000:01:00.0: bios: version 70.24.2e.00.02 ... [ 9.772204] nouveau 0000:01:00.0: fb: 1024 MiB GDDR5 [ 9.777342] ------------[ cut here ]------------ [ 9.782106] refcount_t: increment on 0; use-after-free. [ 9.787522] WARNING:

Add support for reclocking on GK20A, using a statically-defined pstates table. The algorithms for calculating the coefficients and setting the clocks are directly taken from the ChromeOS kernel. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 1 +

Fixes regression introduced in commit 70790f4f "drm/nouveau/clock: pull in the implementation from all over the place" When code was moved from nv50_crtc_set_clock to nvc0_clock_pll_set, the PLLs it is used for got limited to only the first two VPLLs. nv50_crtc_set_clock was only called to change VPLLs, so it didn't limit what it was used for in any way. Since nvc0_clock_pll_set is

Based on the xf86-video-nv code, NFORCE (NV1A) and NFORCE2 (NV1F) have a different way of retrieving clocks. See the nv_hw.c:nForceUpdateArbitrationSettings function in the original code for how these clocks were accessed. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54587 Cc: stable at vger.kernel.org Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- According to several

This used to be done implicitly Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index c5b46e3..9764792 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++

For some reason max_vco was set to a lower value that it can support, which prevented some clock states to be applied. Fix this by setting it to the same value as downstream. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- nvkm/subdev/clock/gk20a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nvkm/subdev/clock/gk20a.c b/nvkm/subdev/clock/gk20a.c index

Signed-off by: Rosen Penev <rosenp at gmail.com> --- drm/nouveau/dispnv04/disp.h | 4 ++-- drm/nouveau/dispnv04/hw.h | 2 +- drm/nouveau/nouveau_bo.h | 2 +- drm/nouveau/nouveau_display.h | 4 ++-- drm/nouveau/nvkm/engine/dma/user.h | 2 +- drm/nouveau/nvkm/subdev/clk/pll.h | 2 +- drm/nouveau/nvkm/subdev/fb/priv.h | 2 +-

Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c | 73 +++++++++++++++--------- drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h | 2 +- drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c | 2 +- 3 files changed, 48 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c

Hey Alex, Thanks. I have a couple of questions and remarks, but really, those should be treated as discussion points rather than anything else. Besides some inline comments, I was curious whether it is not necessary to pause PFIFO and the engines like done with at least NVA3-NVAF? Or is the transition smooth enough? op 10-07-14 09:34, Alexandre Courbot schreef: > Add support for

Remove drm_nouveau_private::fb member and map the piece of VRAM only when accessing VGA fonts. Collect copied code into the static function nouveau_vga_font_io(). Signed-off-by: Pekka Paalanen <pq at iki.fi> --- drivers/gpu/drm/nouveau/nouveau_drv.h | 17 ------- drivers/gpu/drm/nouveau/nouveau_hw.c | 75 +++++++++++++++---------------- drivers/gpu/drm/nouveau/nouveau_state.c |

I have two monitors connected to the PC. One is an AOC 23" (1920 x 1080) and the other is a BenQ 27" (2560 x 1440). Nothing special about them. BenQ has a display port and the AOC uses some sort of DVI adapter. I have this event many times and I captured dmesg twice. At least at one time I captured dmesg my computer was under high load: it had about 15 to 20 windows opened

v2: Check for PFIFO, don't pause if it's not yet running. This should fix reclocking on boot Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/device/nv50.c | 4 +- .../gpu/drm/nouveau/core/include/subdev/clock.h | 4 + drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c | 439

v2: Check for PFIFO, don't pause if it's not yet running. This should fix reclocking on boot v3: Tiny clean up Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/device/nv50.c | 4 +- .../gpu/drm/nouveau/core/include/subdev/clock.h | 4 +

This series does some refactoring in the GK20A's volt and clk drivers (fixing a few things while we are at it) to let GM20B benefit from the GK20A's logic with which it is compatible. GM20B is capable of more sophisticated (and power-efficient) reclocking which will follow later. Even after this more fancy reclocking is merged, the present logic will remain used in the lowest speedo of

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

Patch 1 and 2 implement wait-for-vblank, required to remove flicker when reclocking memory Patch 3 and 4 allow me to do things between waiting for VBLANK and disabling FB, like pause PFIFO and wait for the engines to idle. This minimises the time PFIFO is paused, thus maximises performance. The rest of the patches speak for themselves. As the actual memory reclocking script is still somewhat prone