similar to: [PATCH -next] drm/nouveau: fix build error without CONFIG_IOMMU_API

On Mon, Sep 16, 2019 at 04:35:30PM +0100, Ben Dooks wrote: > On 16/09/2019 16:04, Thierry Reding wrote: > > From: Thierry Reding <treding at nvidia.com> > > > > There are extra registers that need to be programmed to make the level 2 > > cache work on GP10B, such as the stream ID register that is used when an > > SMMU is used to translate memory addresses.

On Mon, Sep 16, 2019 at 05:49:46PM +0200, Thierry Reding wrote: > On Mon, Sep 16, 2019 at 04:35:30PM +0100, Ben Dooks wrote: > > On 16/09/2019 16:04, Thierry Reding wrote: > > > From: Thierry Reding <treding at nvidia.com> > > > > > > There are extra registers that need to be programmed to make the level 2 > > > cache work on GP10B, such as the

From: Joerg Roedel <jroedel at suse.de> Convert the arm-smmu and arm-smmu-v3 drivers to use the probe_device() and release_device() call-backs of iommu_ops, so that the iommu core code does the group and sysfs setup. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- drivers/iommu/arm-smmu-v3.c | 38 ++++++++++-------------------------- drivers/iommu/arm-smmu.c | 39

On Mon, 9 Dec 2019 at 22:00, Thierry Reding <thierry.reding at gmail.com> wrote: > > From: Thierry Reding <treding at nvidia.com> > > Hi Ben, > > here's a revised subset of the patches I had sent out a couple of weeks > ago. I've reworked the BAR2 accesses in the way that you had suggested, > which at least for GP10B turned out to be fairly trivial to

From: Joerg Roedel <jroedel at suse.de> Convert the Mediatek IOMMU driver to use the probe_device() and release_device() call-backs of iommu_ops, so that the iommu core code does the group and sysfs setup. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- drivers/iommu/mtk_iommu.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git

From: Joerg Roedel <jroedel at suse.de> Convert the Mediatek-v1 IOMMU driver to use the probe_device() and release_device() call-backs of iommu_ops, so that the iommu core code does the group and sysfs setup. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- drivers/iommu/mtk_iommu_v1.c | 50 +++++++++++++++--------------------- 1 file changed, 20 insertions(+), 30 deletions(-)

From: Thierry Reding <treding at nvidia.com> This dummy implementation is useful to avoid a dependency on the IOMMU_API Kconfig symbol in drivers that can optionally use the IOMMU API. In order to fully use this, also move the struct iommu_fwspec definition out of the IOMMU_API protected region. Suggested-by: Ben Dooks <ben.dooks at codethink.co.uk> Signed-off-by: Thierry Reding

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

From: Thierry Reding <treding at nvidia.com> Hi, the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why exactly is not clear, but there are slight differences between the SKUs that were tested. It turns out that the biggest issue is that on some devices (e.g. the one that I have), pulsing the GPU reset twice as is done in the current code (once as part of the power-ungate

From: Thierry Reding <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the

On 1/21/20 1:29 PM, akpm at linux-foundation.org wrote: > The mm-of-the-moment snapshot 2020-01-21-13-28 has been uploaded to > > http://www.ozlabs.org/~akpm/mmotm/ > > mmotm-readme.txt says > > README for mm-of-the-moment: > > http://www.ozlabs.org/~akpm/mmotm/ > > This is a snapshot of my -mm patch queue. Uploaded at random hopefully > more than once

On Sun, Jun 10, 2018 at 01:01:31PM +0200, Nicolas Chauvet wrote: > This allows to have the related MODULE_FIRMWARE tag only > on relevant arch (arm64). > This will saves about 400k on initramfs when not relevant > > Signed-off-by: Nicolas Chauvet <kwizart at gmail.com> > --- > drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 2 ++ >

2018-06-11 10:33 GMT+02:00 Thierry Reding <thierry.reding at gmail.com>: > On Sun, Jun 10, 2018 at 01:01:31PM +0200, Nicolas Chauvet wrote: >> This allows to have the related MODULE_FIRMWARE tag only >> on relevant arch (arm64). >> This will saves about 400k on initramfs when not relevant >> >> Signed-off-by: Nicolas Chauvet <kwizart at gmail.com>

This allows to have the related MODULE_FIRMWARE tag only on relevant arch (arm64). This will saves about 400k on initramfs when not relevant Signed-off-by: Nicolas Chauvet <kwizart at gmail.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c | 2 ++ 2 files changed, 4 insertions(+) diff --git

Hi, here is a patch-set to rename iommu_param to dev_iommu and establish it as a struct for generic per-device iommu-data. Also move the iommu_fwspec pointer from struct device into dev_iommu to have less iommu-related pointers in struct device. The bigger part of this patch-set moves the iommu_priv pointer from struct iommu_fwspec to dev_iommu, making is usable for iommu-drivers which do not

From: Thierry Reding <treding at nvidia.com> gp10b doesn't have all the registers that gp102_gr_zbc wants to access, which causes IBUS MMIO faults to occur. Avoid this by using the gp100 variants of grctx and gr_zbc. Signed-off-by: Thierry Reding <treding at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c | 2

GP10B's FB is largely compatible with the GP100 implementation, and only requires a few additional register inits. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/subdev/fb.h | 1 + drm/nouveau/nvkm/subdev/fb/Kbuild | 1 + drm/nouveau/nvkm/subdev/fb/gp10b.c | 38 ++++++++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+) create

From: Thierry Reding <treding at nvidia.com> The low-level Falcon bootstrapping callbacks are expected to return 0 on success or a negative error code on failure. However, the implementation on Tegra returns the ID or mask of the Falcons that were bootstrapped on success, thus breaking the calling code, which treats this as failure. Fix this by making sure we only return 0 or a negative

GP10B's MC is compatible with GP100's, but engines need to be explicitly put out of ELPG during init. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/subdev/mc.h | 1 + drm/nouveau/nvkm/subdev/mc/Kbuild | 1 + drm/nouveau/nvkm/subdev/mc/gp100.c | 17 ++++++++---- drm/nouveau/nvkm/subdev/mc/gp10b.c | 50

GR is similar to GP100, with a few unavailable registers. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/engine/gr.h | 1 + drm/nouveau/nvkm/engine/gr/Kbuild | 1 + drm/nouveau/nvkm/engine/gr/gf100.h | 4 +++ drm/nouveau/nvkm/engine/gr/gp100.c | 13 ++++++-- drm/nouveau/nvkm/engine/gr/gp102.c | 1 + drm/nouveau/nvkm/engine/gr/gp10b.c |