similar to: [Bug 111843] New: Resume fails after suspend with nouveau and Gtx 1050 ti

Displaying 15 results from an estimated 15 matches similar to: "[Bug 111843] New: Resume fails after suspend with nouveau and Gtx 1050 ti"

2019 Sep 27
2
Question on target-features
Hi, In "target-features" list in LLVM-IR, there are "+feature", "-feature". My question is, does "-feature" is equivalent to not specifying a feature at all? For example: *attributes #0 = { "target-cpu"="znver2" "target-features"="+avx -avx2" }* Wheather it is equalent to omitting the avx2 from list? *attributes #0
2019 Sep 27
3
Question on target-features
Ugh, that would be a “yes” then… -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Krzysztof Parzyszek via llvm-dev Sent: Friday, September 27, 2019 10:05 AM To: Dangeti Tharun kumar <cs15mtech11002 at iith.ac.in>; llvm-dev at lists.llvm.org Subject: [EXT] Re:
2019 Sep 27
5
[Bug 111841] New: Setting gamma or color temperature on GK104 causes horizontal artifacts / flickering
https://bugs.freedesktop.org/show_bug.cgi?id=111841 Bug ID: 111841 Summary: Setting gamma or color temperature on GK104 causes horizontal artifacts / flickering Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority:
2019 Sep 27
2
What about multiple MachineMemOperands in one MI (BranchFolding/MachineInstr::mayAlias)?
Hi! Does anyone know how it should be interpreted when one MI has multiple MachineMemOperands? (I've tried to find information but could not find any clear definition.) For example BranchFolder may do things like this (also see https://godbolt.org/z/iphFH4): # *** IR Dump Before Control Flow Optimizer ***: bb.0.entry: ... JCC_1 %bb.2, 5, implicit killed $eflags JMP_1 %bb.1 bb.1.s1:
2019 Sep 27
3
Dovecote IMAPSieve user scripts
Hello, I wonder how to configure IMAPSieve with user scripts. I can't find much information on the internet. I have Sieve and IMAPSieve for spam configured as described in the wiki and it works. Documentation mentions that imapsieve_url has to be set to appropriate ManageSieve server but no further explanation is given. What I want to achieve: let users create their own sieve scripts and
2019 Sep 27
3
DenseMap/ValueMap: is M[New]=M[Old] valid ?
On Thu, 26 Sep 2019, David Blaikie wrote: > I'd be surprised if Clang or GCC's behavior here varied depending on the > size of anything, but maybe? > > In any case, C++17 or so requires the RHS to be evaluated before the LHS for > assignments - so this is now /always/ wrong, not just unspecified (which, I > guess, also always wrong... just sometimes accidentally right)
2019 Sep 27
5
[RFC] Propeller: A frame work for Post Link Optimizations
On Thu, Sep 26, 2019 at 5:13 PM Eli Friedman <efriedma at quicinc.com> wrote: > > > -----Original Message----- > > From: Sriraman Tallam <tmsriram at google.com> > > Sent: Thursday, September 26, 2019 3:24 PM > > To: Eli Friedman <efriedma at quicinc.com> > > Cc: Xinliang David Li <xinliangli at gmail.com>; llvm-dev <llvm-dev at
2019 Sep 25
2
Remove obsolete debug info while garbage collecting
On Tue, Sep 24, 2019 at 11:22 PM Rui Ueyama via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Alexay, > > Thank you for the detailed explanation. The other question I have is, as > discussed above, about dsymutil. You said that dsymutil is not usable at > link-time. What does that mean? If we only have to emit an output file in > the usual way and then automatically
2019 Sep 27
0
Is Nouveau really using the io_reserve_lru?
Am 27.09.2019 20:07 schrieb Ilia Mirkin <imirkin at alum.mit.edu>: On Thu, Sep 26, 2019 at 5:44 PM Ben Skeggs <skeggsb at gmail.com> wrote: > > On Tue, 24 Sep 2019 at 22:19, Christian König > <ckoenig.leichtzumerken at gmail.com> wrote: > > > > Hi guys, > > > > while working through more old TTM functionality I stumbled over the > >
2019 Sep 27
2
Maybe a TableGen bug?
Hi, Here's llvm-tblgen -print-records message: def LOADbos { // Instruction ABCInst ABCInstMMEMrr field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2019 Sep 27
0
Dovecote IMAPSieve user scripts
> I wonder how to configure IMAPSieve with user scripts. I can't find much > information on the internet. try to enable managesieve: service managesieve-login { inet_listener sieve { port = 4190 } } https://wiki2.dovecot.org/Pigeonhole/ManageSieve/Configuration <https://wiki2.dovecot.org/Pigeonhole/ManageSieve/Configuration> Roundcube or Thunderbird with Sieve plugin
2005 Feb 23
13
Snort and Shorewall
Hello I am looking for a way to have snort to dynamically update my shorewall config. I have seen software out there but I would like to see if anyone had tried this first. Aslo I would like to know if there is a way clear the Netfilter tables when I do a shorewall restart. The reason being is that when I make a change to my firewall setting I want all connections to have to re-establish
2019 Sep 27
3
What about multiple MachineMemOperands in one MI (BranchFolding/MachineInstr::mayAlias)?
On 9/27/19 7:33 AM, Matt Arsenault via llvm-dev wrote: > > >> On Sep 27, 2019, at 09:07, Björn Pettersson A via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Obviously we do not store into two locations (it is still a single >> two byte store). >> So is it (always) correct to interpret the list of
2019 Sep 27
3
UPS not recognized
Hello, Replaced UPS Kstar Micropower Micro 1200 (managed via blazer_usb) with https://www.njoy.ro/UPS/horus-plus-2000. The latter doesn't seem to be supported. 1. I tried blazer_usb and usbhid-ups. Any other suggestions? 2. What would be needed to get it supported by NUT? ======== HW ======== HP Microserver Gen 8 ======== UPS ======== Working:Kstar Micropower Micro
2019 Sep 27
4
Dealing with boolean values in GlobalISel
Hi, I’ve been thinking about what the strategy to use for boolean values in GlobalISel. There are a few semantic and mechanical issues I’ve encountered. For background, on AMDGPU, there are two kinds of bool/s1 values. Contextually, a real boolean value will either be a 1-bit scalar condition (in a non-allocatable physical condition register, which will need to be copied to an allocatable class