similar to: [RFC PATCH] clk: Remove BYPASS_PLL_CHECK from PLLs

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

Corresponds with GT215. Don't rely on the lock test logic being unconditionally enabled, and disable test logic when done (presumably to save power). Warn when locking fails. Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 15 ++++++++++++--- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 15 ++++++++++++--- 2 files changed, 24

Corresponds with GT215. Don't rely on the lock test logic being unconditionally enabled, and disable test logic when done (presumably to save power). v2: Remove warning, nvkm_msec already warns on time-out Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 8 +++++++- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 8 +++++++- 2

On Thu, Sep 12, 2019 at 3:00 PM Karol Herbst <kherbst at redhat.com> wrote: > > taken from nvgpu > > Signed-off-by: Karol Herbst <kherbst at redhat.com> > --- > drm/nouveau/nvkm/subdev/pci/gk104.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drm/nouveau/nvkm/subdev/pci/gk104.c b/drm/nouveau/nvkm/subdev/pci/gk104.c > index

taken from nvgpu Signed-off-by: Karol Herbst <kherbst at redhat.com> --- drm/nouveau/nvkm/subdev/pci/gk104.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drm/nouveau/nvkm/subdev/pci/gk104.c b/drm/nouveau/nvkm/subdev/pci/gk104.c index 6aeb07fe4..2d1fa67eb 100644 --- a/drm/nouveau/nvkm/subdev/pci/gk104.c +++ b/drm/nouveau/nvkm/subdev/pci/gk104.c @@ -23,6 +23,8 @@ */ #include

Patch "ltc/gm107: use nvkm_mask to set cbc_ctrl1" sets the 3rd bit of the CTRL1 register instead of writing it entirely in gm107_ltc_cbc_clear(). As a counterpart, gm107_ltc_cbc_wait() must also be modified to wait on that single bit only, otherwise a timeout may occur if some other bit of that register is set. This happened at least on GM206 when running glmark2-drm. While we are at

The IRQ mask of the PMU falcon was left - replace it with the proper irq_mask variable. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/secboot/base.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/secboot/base.c b/drm/nouveau/nvkm/subdev/secboot/base.c index b718ba79177c..05c62549c39b 100644 ---

Following a series of three patches, two of which have been sitting in my tree for a while, the third is the result of some inspection of an NV134 BIOS that seems to use the 0xaf upcode to upload training patterns. Please test! Roy Ps. Sorry they come from yet another e-mail address. My previous provider, eclipso, actively blocks users of git send-email. Inquiries fall on deaf ears, hence I

The nouveau driver, in the Linux 3.7 days, used to try and set the AVI InfoFrame based on the selected display mode. These days, it uses a fixed set of InfoFrames. Start to correct that, by providing a mechanism whereby InfoFrame data may be passed to the NVKM functions that do the actual configuration. At this point, only establish the new parameters and their parsing, don't actually use

"hiding" unconditional assignments in the if() parentesis makes for hard to read code and has no advantage over placing these assignments in proper formated lines before the if() statement. Simply move those lines out. Before sending out roughly 20 patches to fix the roughly 50 cases - all in the nouveau driver. I would like to know if this will be accepted at all. Signed-off-by:

Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> ---

Hello Ben Skeggs, The patch a9c44a88ca2f: "drm/nouveau/disp/nv50-: add channel interfaces to control error interrupts" from May 8, 2018, leads to the following static checker warning: drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c:55 gf119_disp_chan_intr() warn: should '1 << chan->chid.user' be a 64 bit type?

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 2 +- drm/nouveau/nvkm/subdev/fb/ramgk104.c | 8 ++++---- drm/nouveau/nvkm/subdev/therm/nv40.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index ddaa16a..ad0a6cf 100644 ---

Hello Ben Skeggs, The patch 88524bc06926: "drm/nouveau/devinit: move simple pll setting routines to devinit" from Mar 5, 2013, leads to the following static checker warning: drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c:53 nv50_devinit_pll_set() info: return a literal instead of 'ret' drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 34 int 35

From: Colin Ian King <colin.king at canonical.com> The constant values being shifted are 32 bit integers and may potentially overflow on the shift. Avoid this potential overflow by making them unsigned long long values before the shift. Detected by CoverityScan, CID#1469383, 1469400 ("Unintentional integer overflow") Signed-off-by: Colin Ian King <colin.king at

I hit this while loop in an error state of the gpu Signed-off-by: Karol Herbst <nouveau at karolherbst.de> --- drm/nouveau/nvkm/subdev/pmu/base.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/pmu/base.c b/drm/nouveau/nvkm/subdev/pmu/base.c index fafbe2a..398b6a8 100644 --- a/drm/nouveau/nvkm/subdev/pmu/base.c +++

> Emil Velikov <emil.l.velikov at gmail.com> hat am 14. November 2015 um 23:44 > geschrieben: > > On 14 November 2015 at 19:51, Karol Herbst <nouveau at karolherbst.de> wrote: > > I hit this while loop in an error state of the gpu > > > > v2: unlock mutex only if reply == true > > > > Signed-off-by: Karol Herbst <nouveau at

I hit this while loop in an error state of the gpu v2: unlock mutex only if reply == true Signed-off-by: Karol Herbst <nouveau at karolherbst.de> --- drm/nouveau/nvkm/subdev/pmu/base.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/pmu/base.c b/drm/nouveau/nvkm/subdev/pmu/base.c index 81a5583..eb248fd 100644 ---