similar to: Questions on Maxwell 2nd Gen Compute Kernels/Shaders

Hi folks, ARM v8.5 introduces the Memory Tagging Extension (MTE), a hardware that allows for detection of memory safety bugs (buffer overflows, use-after-free, etc) with low overhead. So far, MTE support is implemented in the Scudo hardened allocator (compiler-rt/lib/scudo/standalone) for heap, and stack allocation is implemented in LLVM/Clang behind -fsanitize=memtag

Hi David, Does the tagging of these hidden symbols only protect against RW > primitives without a similar ldg? If I knew the address of the hidden > symbol I could presumably use the same sequence, but I think I'm > stretching what memory tagging is supposed to protect against. I might be missing your point here - but don't forget that the local globals are always PC-relative

> I might be missing your point here - but don't forget that the local globals are always PC-relative direct loads/stores. I did forget! Thanks for clarifying, now I understand. On Fri, 18 Sep 2020 at 20:51, Evgenii Stepanov <eugenis at google.com> wrote: > > > > On Fri, Sep 18, 2020 at 12:18 PM Mitch Phillips via llvm-dev <llvm-dev at lists.llvm.org> wrote:

> > note: these bits are not really reserved for os or processor > specific use in ELF. in practice they are processor specific > so it will be STO_AARCH64_TAGGED. > Correct. note2: undefined symbol references will need correct marking > too if objects may get copy relocated into the main exe and > linkers should check if definitions match references. Yep - at this point I

Generated with envysched. Tested by running rendercheck from piglit, running mplayer -vo xv, and staring at gnome-shell. Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com> --- src/shader/exac8nv110.fp | 11 ++++---- src/shader/exac8nv110.fpc | 22 ++++++++-------- src/shader/exacanv110.fp | 11 ++++---- src/shader/exacanv110.fpc | 22 ++++++++-------- src/shader/exacmnv110.fp | 10

https://bugs.freedesktop.org/show_bug.cgi?id=96355 Bug ID: 96355 Summary: Performance: extra&costly SSBO validation even when SSBO aren't used Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component:

Hello, I trying TSAN on Darwin on LLVM itself (sanitizing multi-threaded ThinLTO link). However I see two main issues on my debug build: 1) Statistics: the pre/post increment is not safe, it seems to be acknowledge in the code itself: // FIXME: This function and all those that follow carefully use an // atomic operation to update the value safely in the presence of // concurrent

This series is to allow NVIDIA chips with shared memory to operate more efficiently (and to operate at all once we disable VRAM from the kernel driver) by allowing nouveau_screen to specify a domain to use for objects originally allocated into VRAM. If the domain is not overridden, the default NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be used in place of

On Mon, May 19, 2014 at 12:16 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/gallium/drivers/nouveau/nvc0/nvc0_video.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_video.c b/src/gallium/drivers/nouveau/nvc0/nvc0_video.c > index 5871f59..c9ab13a

Hello, The method we previously used on Fermi and Kepler (0x142c) to flush the VBO cache before draw appears to be gone on Maxwell. Is there a replacement method we should use? (Or perhaps that method was never meant for VBO cache flush and instead flushed something related to the vertex quarantine area defined by 0x17bc/0x17c0/0x17c4, which in turn is gone on Maxwell?) Thanks for any light you

On Tue, Feb 23, 2016 at 06:55:59PM +0900, Alexandre Courbot wrote: > Hi linux-firmware maintainers, > > The following changes since commit f66eccaab7d605d433cb82e389441b21ec99b40f: > > Update Intel OPA hfi1 firmware (2016-02-15 08:34:16 -0500) > > are available in the git repository at: > > https://github.com/Gnurou/linux-firmware.git secboot > > for you

Thanks for the update. Are you updating nouveau for GK208 and GM206? Regards, On Tue, Feb 23, 2016 at 4:11 PM, Kyle McMartin <kyle at infradead.org> wrote: > On Tue, Feb 23, 2016 at 06:55:59PM +0900, Alexandre Courbot wrote: > > Hi linux-firmware maintainers, > > > > The following changes since commit > f66eccaab7d605d433cb82e389441b21ec99b40f: > > > >

Signed-off-by: Karol Herbst <nouveau at karolherbst.de> --- drm/nouveau/nvkm/subdev/fb/gm107.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/subdev/fb/gm107.c b/drm/nouveau/nvkm/subdev/fb/gm107.c index 2a91df8..9cc7e61 100644 --- a/drm/nouveau/nvkm/subdev/fb/gm107.c +++ b/drm/nouveau/nvkm/subdev/fb/gm107.c @@ -29,7 +29,7 @@ gm107_fb = { .dtor =

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/nouveau_copy.c | 2 ++ src/nvc0_accel.c | 10 +++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c index c139de6..7118a7a 100644 --- a/src/nouveau_copy.c +++ b/src/nouveau_copy.c @@ -42,6 +42,8 @@ nouveau_copy_init(ScreenPtr pScreen) int engine; Bool

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Untested. src/nouveau_copy.c | 2 ++ src/nouveau_exa.c | 1 + src/nv_accel_common.c | 1 + src/nv_driver.c | 3 +++ src/nv_type.h | 1 + src/nvc0_accel.c | 6 ++++++ 6 files changed, 14 insertions(+) diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c index 7118a7a..7fbcc87 100644 --- a/src/nouveau_copy.c

Well, you are most likely using the CPU for decoding here. Currently nobody is working on that, because this is quite a big and challenging project. We have an open project idea regarding this for EVoC and GSoC though: "Maxwell Accelerated Video Decoding" https://www.x.org/wiki/SummerOfCodeIdeas/ On Thu, Nov 30, 2017 at 1:18 PM, Christoph Böhmwalder <christoph at boehmwalder.at>

Hello, I got some doubts on how texture modes work on TEX, TEXS, TLD4, etc instructions. I got: DC, AOFFI, NDV, NODEP, MZ, PTP modes as well as LZ Mode. How does this work or change the behavior of the texture instruction. So far of those I know AOFFI defines an Offset but I'm on blanks for the rest. -------------- next part -------------- An HTML attachment was scrubbed... URL:

So I have been going on over the documentation trying to figure out the exact layout of Pitch Linear Textures and find some missing values. First Question: What's the correct layout of pitch linear textures in memory? Is padding of the pitch added at start or at the end? Do they have some kind of header? Currently I see them as a normal texture matrix with just pitch at the end of each row

Signed-off-by: Faris Alsalama <farisbenbrahem at gmail.com> --- drivers/gpu/drm/nouveau/nouveau_backlight.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c index 89eb460..dd1cc9b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_backlight.c +++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c @@ -232,6

0xc0b5 is not in rnndb, I guess it should be GP100_COPY, right? Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> On 10/27/2016 04:02 PM, Ilia Mirkin wrote: > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nouveau_copy.c | 2 ++ > src/nvc0_accel.c | 10 +++++++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git