similar to: Questions on Falcon Command Processor

As it turns out, with the proprietary firmware, the VP3 and VP4 interfaces are identical. Furthermore, this is all already implemented for nvc0. So these patches (a) move the easily sharable bits of the nvc0 implementation into the nouveau directory, and then (b) implement the other parts in nv50. The non-shared parts are still largely copies, but there are some differences, not the least of which

Hi guys how are you doing? I have some questions on how the GPU handles syncpoints from the commandlist. I do know the register 0xB2 is the one written in the Maxwell3D Engine. As far as I know bits 0:15 are the syncpoint id, bit 16 is unknown for me, bit 20 is increment? What other bits are set and what should be done on increment? Thanks in advance. -------------- next part -------------- An

Create the ref_bo without any storage type flags set for now. The issue probably arises from our use of the additional buffer space at the end of the ref_bo. It should probably be split up in the future. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Tested-by: Martin Peres <martin.peres at labri.fr> Cc: "10.0" <mesa-stable at lists.freedesktop.org> ---

On Thu, Nov 21, 2013 at 5:22 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > On Thu, Nov 21, 2013 at 5:07 PM, Benjamin Morris <bmorris at nvidia.com> wrote: >> On 11/19/2013 08:16 PM, Ilia Mirkin wrote: >>> Hello, >>> >>> I hope this is an appropriate style of request for this forum. I added >>> code to support video decoding on the tesla

I'm currently running tests to document PASCAL's ISA on Cuda but I've come to a dead end with the IPA instruction. I've tried searching around Nouveau's codebase for clues but I've fallen short from it. Could someone reference me in the right direction? -- Atentamente, *Fernando A. Sahmkow* *Correo*: fsahmkow27 at gmail.com -------------- next part -------------- An HTML

On Fri, Dec 6, 2013 at 7:36 PM, Benjamin Morris <bmorris at nvidia.com> wrote: > I've gathered a few hints regarding H264 video decoding on our hardware. Hopefully some of them will be useful. Very useful! > > First off, regarding naming in general. Our internal names for our video engines differ from the names you've been using. Below is a translation map between the

Hello Alexandre Courbot, The patch 5429f82f3415: "drm/nouveau/secboot: add gp102/gp104/gp106/gp107 support" from Jan 26, 2017, leads to the following static checker warning: drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c:63 gp102_run_secure_scrub() warn: passing zero to 'PTR_ERR' drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c 46 static int 47

So I'm trying to track an special value in IPA instruction generation. https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp#L2561 Register on 0x14 (20) is set to some source on "insn->op == OP_PINTERP" I have found while emulation that such value can be set sometimes to FragCoord.w, I don't however know what that value is and

Create the ref_bo without any storage type flags set for now. This can probably be split up somehow later on, but this seems to work. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.0" <mesa-stable at lists.freedesktop.org> --- Would be great if someone could see if this also makes MPEG4 work on NVA3+. In order to do that, remove the if (chipset < 0xc0)

Hello, I got some doubts on how texture modes work on TEX, TEXS, TLD4, etc instructions. I got: DC, AOFFI, NDV, NODEP, MZ, PTP modes as well as LZ Mode. How does this work or change the behavior of the texture instruction. So far of those I know AOFFI defines an Offset but I'm on blanks for the rest. -------------- next part -------------- An HTML attachment was scrubbed... URL:

Thanks for the last info it was truely helpful. Anyways, I'm currently trying to implement 3D textures into yuzu, as far as I know they are twiddled in a different manner to 2D textures. Could one of you guys point me in the right direction? I've been meddling around: https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nv50/nv50_tex.c but I can't see where the

So there's a register in Render Targets called Array Mode: https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_3d.xml#L289 We've witnessed values of 1 and 6 (array mode -> layers) but we can't tell their meaning. Do you guys got any related info? Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed... URL:

I'm currently implementing mipmaps but I have a set of troubles guessing the block height and block depth of them. According to https://envytools.readthedocs.io/en/latest/hw/memory/g80-surface.html#textures-mipmapping-and-arrays the texture unit auto resizes mipmaps' blocks but how do I know how many blocks each one uses? I'm currently using this algorithm: u32 height =

So I have been going on over the documentation trying to figure out the exact layout of Pitch Linear Textures and find some missing values. First Question: What's the correct layout of pitch linear textures in memory? Is padding of the pitch added at start or at the end? Do they have some kind of header? Currently I see them as a normal texture matrix with just pitch at the end of each row

Hi guys again. A homebrew developer (homebrew is custom software made for the switch using openGL under nouveau) reported to me that 'glGenerateMipmap' wasn't working on yuzu (Nintendo Switch emulator). I looked into it and I noticed all the triangle data used by nouveau to render the mipmaps was all zeroed out, meaning that probably we don't implement the mechanism you guys use to

Hello everyone, I've been trying to adapt a switch emulator to emulate nouveau's compute. We've been told some things like indirect dispatch use the MME in Nouveau, however, looking at NVIDIA's open gpu documentation there's no MME in compute engine since Kepler. https://github.com/NVIDIA/open-gpu-doc/blob/master/classes/compute/clb1c0.h MME for compute should still exist

So we have been busy implementing the compute engine lately but we have discovered a few issues with Compute Shaders. I hope you guys can answer some questions. 1st How do I determine the size of Compute Shaders/Kernel Local Memory ? In Pipeline shaders the size is included in the header but Compute Kernels don't have a header, so how do I determine how much local memory it uses? In case I

So I have been implementing syncing mechanisms to yuzu's switch emulator, aka Tegra X1 emulation and I already have: Semaphores, Syncpoints and Queries to some extent. I'm missing the barriers (GPU waits for CPU): I got this from RE: Barrier mode has priority (from highest to lowest): 1) 0x08 sets needsWfi=0 -> highest priority, does puller refcnt + split(0,0) + 0x100 NoOperation + rest

So we are currently doing tests and complying with them in our Emulator. Currently the conditional rendering test does not pass (no wonder we not even implement it). I've been looking at the current documentation https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_3d.xml#L796 So far I don't understand how the cond address is used and to what it's compared.

Apparently some players are ill-prepared for us claiming that a decoder exists only to have creating it fail, and express this poor preparation with crashes (e.g. flash). Check that firmware is there to increase the chances of there being a high correlation between reported capabilities and ability to create a decoder. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: 10.0 10.1