similar to: Question on Render Targets Register: Array Mode

So I have been going on over the documentation trying to figure out the exact layout of Pitch Linear Textures and find some missing values. First Question: What's the correct layout of pitch linear textures in memory? Is padding of the pitch added at start or at the end? Do they have some kind of header? Currently I see them as a normal texture matrix with just pitch at the end of each row

So we are currently doing tests and complying with them in our Emulator. Currently the conditional rendering test does not pass (no wonder we not even implement it). I've been looking at the current documentation https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_3d.xml#L796 So far I don't understand how the cond address is used and to what it's compared.

Hi guys how are you doing? I have some questions on how the GPU handles syncpoints from the commandlist. I do know the register 0xB2 is the one written in the Maxwell3D Engine. As far as I know bits 0:15 are the syncpoint id, bit 16 is unknown for me, bit 20 is increment? What other bits are set and what should be done on increment? Thanks in advance. -------------- next part -------------- An

I'm currently running tests to document PASCAL's ISA on Cuda but I've come to a dead end with the IPA instruction. I've tried searching around Nouveau's codebase for clues but I've fallen short from it. Could someone reference me in the right direction? -- Atentamente, *Fernando A. Sahmkow* *Correo*: fsahmkow27 at gmail.com -------------- next part -------------- An HTML

So I'm trying to track an special value in IPA instruction generation. https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp#L2561 Register on 0x14 (20) is set to some source on "insn->op == OP_PINTERP" I have found while emulation that such value can be set sometimes to FragCoord.w, I don't however know what that value is and

Sorry for the unresponsiveness. To the problem: I think the 'stray character' is the 'V', as it's the newer one of the options used here (the dot notation is required by the 'k' option and seems to be supported ever since the release of GNU sort). - http://git.savannah.gnu.org/cgit/coreutils.git/commit/?id=4c9fae4e97d95a9f89d1399a8aeb03051f0fec96 Newer versions of (GNU)

Hello, I got some doubts on how texture modes work on TEX, TEXS, TLD4, etc instructions. I got: DC, AOFFI, NDV, NODEP, MZ, PTP modes as well as LZ Mode. How does this work or change the behavior of the texture instruction. So far of those I know AOFFI defines an Offset but I'm on blanks for the rest. -------------- next part -------------- An HTML attachment was scrubbed... URL:

Thanks for the last info it was truely helpful. Anyways, I'm currently trying to implement 3D textures into yuzu, as far as I know they are twiddled in a different manner to 2D textures. Could one of you guys point me in the right direction? I've been meddling around: https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nv50/nv50_tex.c but I can't see where the

I'm currently implementing mipmaps but I have a set of troubles guessing the block height and block depth of them. According to https://envytools.readthedocs.io/en/latest/hw/memory/g80-surface.html#textures-mipmapping-and-arrays the texture unit auto resizes mipmaps' blocks but how do I know how many blocks each one uses? I'm currently using this algorithm: u32 height =

So now I'm to looking to implement NVDec and as far as I know the game submits a series of commands to the service. This commands are processed by Falcon and then it does its magic. Do you guys got any RE on Falcon commands and how they execute different workloads ? -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi guys again. A homebrew developer (homebrew is custom software made for the switch using openGL under nouveau) reported to me that 'glGenerateMipmap' wasn't working on yuzu (Nintendo Switch emulator). I looked into it and I noticed all the triangle data used by nouveau to render the mipmaps was all zeroed out, meaning that probably we don't implement the mechanism you guys use to

Hello everyone, I've been trying to adapt a switch emulator to emulate nouveau's compute. We've been told some things like indirect dispatch use the MME in Nouveau, however, looking at NVIDIA's open gpu documentation there's no MME in compute engine since Kepler. https://github.com/NVIDIA/open-gpu-doc/blob/master/classes/compute/clb1c0.h MME for compute should still exist

On Mon, 13 May 2024 09:54:27 -0500 (CDT) luke-tierney--- via R-devel <r-devel at r-project.org> wrote: > Looks like I added that warning 22 years ago, so that should be enough > notice :-). I'll look into removing it now. Dear Luke, I've got a somewhat niche use case: as a way of protecting myself against rogue *.rds files and vulnerabilities in the C code, I've been

So we have been busy implementing the compute engine lately but we have discovered a few issues with Compute Shaders. I hope you guys can answer some questions. 1st How do I determine the size of Compute Shaders/Kernel Local Memory ? In Pipeline shaders the size is included in the header but Compute Kernels don't have a header, so how do I determine how much local memory it uses? In case I

So I have been implementing syncing mechanisms to yuzu's switch emulator, aka Tegra X1 emulation and I already have: Semaphores, Syncpoints and Queries to some extent. I'm missing the barriers (GPU waits for CPU): I got this from RE: Barrier mode has priority (from highest to lowest): 1) 0x08 sets needsWfi=0 -> highest priority, does puller refcnt + split(0,0) + 0x100 NoOperation + rest

Hello Dan, thanks for your input, I?ve tried to remove ?V' from sort -f -k 4.1,4.5rV -k 5n -t @ - command line => No more ?stray character? ! But I?m still stuck after with the : make: *** No rule to make target `-eindex.html', needed by `ups-html.txt'. Stop. Any idea here? > Le 3 d?c. 2014 ? 01:22, hyouko at gmail.com a ?crit : > > Sorry for the unresponsiveness. >

The headers hadn't been regenerated in a long time and had seen a number of manual modifications. A few changes: - remove nvc0_2d entirely, use the nv50 header which has the nvc0 values too - remove 3ddefs, it's identical to the nv50 file - move macros out into a separate file Also the upstream rnndb changed the overall chip naming convention; this was fixed up manually in the

On Sat, 11 May 2024, Peter Langfelder wrote: > On Sat, May 11, 2024 at 9:34?AM luke-tierney--- via R-devel > <r-devel at r-project.org> wrote: >> >> On Sat, 11 May 2024, Travers Ching wrote: >> >>> The following code snippet causes R to hang. This example might be a >>> bit contrived as I was experimenting and trying to understand >>>

https://bugs.freedesktop.org/show_bug.cgi?id=92971 --- Comment #4 from Ilia Mirkin <imirkin at alum.mit.edu> --- Nov 14 19:06:12 hpprol2 kernel: nouveau 0000:0a:00.0: fifo: PBDMA0: 80000000 [] ch 30 [007e6ab000 kscreenlocker_g[4257]] subc 6 mthd 2878 data a0c02020 A few things wrong with this picture... first off, nouveau never uses subchannel 6. Method 2878 is: lookup -a c8 -d SUBCHAN --

These are copied directly from the mesa repository. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++ src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++---------------- 2 files changed, 892 insertions(+), 340 deletions(-) create mode 100644 src/hwdefs/gm107_texture.xml.h diff --git